A signal generator responsive to a normal mode signal by generating control signals for displaying low luminance foreground pixels and high luminance background pixels. In addition, the signal generator is responsive to a high intensity mode signal by generating control signals for displaying zero luminance foreground pixels and high luminance background pixels.

A graphic display circuit for driving a graphic display comprises a programmable character generator for storing character font data, a video RAM for storing display code data corresponding to characters in said font, an attribute RAM for storing block selection data for selecting one of the blocks of the character generator defining attributes of the character font data, and a controller for controlling the video RAM and attribute RAM.

The line size of character lines constituting a page of print paper is compared with the limited line size. If a line has its line size larger than the limited line size, it is divided into several lines having a smaller line size. An edit control circuit appends a divisional character code to each divided portion of a character which is divided into several lines. An expansion control circuit receives a divisional character code, extracts the divided portion of the character from the patterns of available characters and writes it into a line buffer memory. Patterns in the line buffer memory are written sequentially into a page memory which stores patterns of characters printed in a page of print paper.

A scanning CRT graphics video display system is disclosed in which a graphics display controller reads formatted information signals into a refresh memory in a read-modify-wire mode and reads the stored information out of the refresh memory in a display mode. During the display mode the information in the memory is provided on a common data bus for sequential reading into four different shift registers having different bit capacities with the different bit capacities effectively implementing predetermined delays such that the shift registers will properly simultaneously read out the information that was sequentially loaded into the shift registers. A programmable logic sequencer provides address select signals in addition to address signals provided by the graphics display controller so as to address four different memory planes in the refresh memory, and the address select signals are also utilized to sequentially enable the loading of the four shift registers. The logic sequencer provides a clock timing signal to the controller for controlling the frequency of operation thereof. During the display mode the clock frequency is provided at a first frequency while during the read-modify-write mode, which occurs during video blanking, the sequencer provides a substantially higher frequency clock signal to the controller to implement rapid reading of information into the refresh memory.

There is provided a flat panel display control device which has the compatibility with CRT display and the function of displaying each character with plurality of dots. A flat panel display apparatus incorporating a video memory (3) for storing the character code and the attribute code data, a character generator (6) for generating a character font data correspondent to the said character code, an attribute register (11) for connecting to the said video memory and for latching the said attribute code, and an attribute control means for modifying the attribute code supplied through the said attribute register according to the necessity and for attribute-processing the character font data generated by the said character generator according to the modified data.