Signal detector of magnetic disk apparatus

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BACKGROUND OF THE INVENTION

The present invention relates to a pulse circuit of a magnetic disk apparatus, which converts a peak position of a read signal from a magnetic head to a pulse signal serving as a digital signal.

In general, the data read operation in a magnetic disk apparatus is performed by a readout circuit which includes a pulse circuit. FIG. 1 illustrates a typical readout circuit. Data recorded on a magnetic disk is detected by a magnetic head 1 and is produced as a read signal (head reproduction signal) of an analog signal (voltage signal). The read signal is then amplified by a pre-amp 3, and head noise, ambient noise and circuit noise of the amplified read signal are removed by a low-pass filter (LPF) 5. The filtered signal is differentiated by a differentiator 7. The differential signal is then quantized by a signal detector. Finally, the quantized (or digital) signal is supplied as read data to a controller of the magnetic disk apparatus.

The signal detector (mentioned above) is used to convert a peak position of the read signal to a pulse signal (which serves as a digital signal) and as such is essential to the stable reading of data. In the typical signal detector, an analog signal (differential signal) c obtained by differentiating the read signal is supplied to one input terminal of a comparator 11. A signal having a phase opposite to that of the differential signal c is supplied to the other input terminal thereof. A signal a, having a phase opposite to that of the read signal, is applied to comparator 13. the comparator 13 generates a pulse signal b which rises when the read signal a exceeds a predetermined voltage level TH+ and which falls when the read signal a is less than the predetermined voltage level TH-.

The pulse signal b is supplied to a delay line 17 through an inverter 15 and is delayed by the delay line 17 for a predetermined delay time. This delayed signal is inverted by an inverter 19, which produces a signal e. The signal e is supplied to a data input terminal D of a D-type flip-flop 21. In FIG. 1, reference numerals R1, R2 and R3 denote resistors and reference symbols +V and -V denote voltages.

The comparator 11 produces pulse signals d and f, which rise and fall in response to a zero-crossing of the differential signal c, as shown in FIGS. 2E and 2G, respectively. Pulse signal f is an inverted signal of pulse signal d. The differential signal c is obtained by delaying, for a given delay time, an analog signal c' (see FIG. 2C) which has zero-crossing points respectively corresponding to the positive and negative peaks of the read signal a, thus representing the differentiated read signal. Pulse signal d is supplied to one input terminal of NAND gate 23, and pulse signal f is supplied to one input terminal of NAND gate 25. An output (Q output of FIG. 2I) signal h from the flip-flop 21 is supplied to the other input terminal of NAND gate 23, and an output (Q output of FIG. 2H) signal g from the flip-flop 21 is supplied to the other input terminal of NAND gate 25. The output signals from NAND gates 23 and 25 are supplied to NAND gate 27.

An output signal i (FIG. 2J) from NAND gate 27 is supplied as a clock signal to a clock input terminal CLK of the flip-flop 21. The flip-flop 21 supplies output signals g and h (also discussed above) to a logic circuit 29 (FIG. 1) in synchronism with the clock signal i. The logic circuit 29 generates a pulse signal j having the waveform shown in FIG. 2K (i.e., the digital signal representing the zero-crossing points of the differential signal c which correspond to the peaks of the read signal a). The pulse signal j is regarded as the above-mentioned read data. The logic circuit 29 is constituted by inverters 31, 33 and 35, NAND gates 37, 39 and 41, a delay line 43, and so on.

The pulse circuit having the configuration described above produces a conversion of the read data from the magnetic head to a digital signal. However, according to the conventional system described above, unnecessary zero-crossing points x occur in the differential signal c, as shown in FIG. 2D. Unnecessary pulse signals Px occur in the output signals d, f from the comparator 11. For this reason, a pulse signal i having an insufficient pulse width is often supplied, as the clock signal, to the flip-flop 21. Subsequently, a race condition occurs in the flip-flop 21, and output signals g and h become unstable. These unstable signals increase the error rate and degrade reliability of the magnetic disk apparatus.

SUMMARY OF THE INVENTION

A primary object of the present invention is to provide a signal detector for the readout circuit of a magnetic disk apparatus, wherein the peak of a read signal read out from a magnetic head is properly converted to a pulse signal serving as a digital signal, to accurately produce read data and, hence, to improve reliability of the magnetic disk apparatus.

To achieve the above object, a signal detector of a magnetic disk apparatus is provided, which has a magnetic head for performing the data read/write operation and a differentiator circuit for differentiating an analog signal read out from said magnetic head; said signal detector comprising:

means, coupled to said differentiator circuit, for detecting a ramp state of the waveform of an output from the magnetic head and the zero-crossing point of the output therefrom;

data generating means for generating a signal corresponding to a true peak of the output from the magnetic head;

gate enable signal generating means, coupled to the output from the magnetic head, for generating a signal enabling the detecting means to supply an output to the data generating means; and

gate disable signal generating means for prohibiting the output from the detecting means from being supplied to the data generating means, in accordance with the output from the gate enable signal generating means and the output from the data generating means;

the data generating means being coupled to said detecting means, said gate enable signal generating means and said gate disable signal generating means.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and features of the present invention will be apparent from the following description, in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram illustrating a pulse circuit of a conventional magnetic disk apparatus;

FIGS. 2A through 2K are timing charts of various signals of the pulse circuit shown in FIG. 1, in which FIG. 2A shows a read signal a from the magnetic head, FIG. 2B shows a signal b obtained by pulse-shaping the read signal a at a predetermined threshold value, FIG. 2C shows an analog signal c' having zero-crossing points corresponding to the peaks of the read signal a, FIG. 2D shows a differential signal c, FIG. 2E shows a pulse signal d which rises in response to the zero-crossing point of the differential signal c, FIG. 2F shows an inverted signal e obtained by inverting the delayed signal from a delay line 17 by means of an inverter 19, FIG. 2G shows a pulse signal f which falls in response to the zero-crossing point of the differential signal c, FIG. 2H shows a Q output signal g from a flip-flop 21, FIG. 2I shows a Q output signal h from the flip-flop 21, FIG. 2J shows a clock signal i from NAND gate 27, and FIG. 2K shows a read data signal j;

FIG. 3 is a circuit diagram illustrating a pulse circuit of a magnetic disk apparatus according to an embodiment of the present invention; and

FIGS. 4A through 4L are timing charts of various signals of the pulse circuit shown in FIG. 3, in which FIG. 4A shows a read signal a from a magnetic head, FIG. 4B shows a signal b obtained by pulse-shaping the read signal a at a predetermined threshold value, FIG. 4C shows a differential signal c, FIG. 4D shows a pulse signal d which rises in response to a zero-crossing point of the differential signal c, FIG. 4E shows a pulse signal f which falls in response to the zero-crossing point of the differential signal c, FIG. 4F shows an inverted signal e obtained by inverting a delayed signal from a delay line 17 by means of the inverter 19, FIG. 4G shows a signal m obtained by gating the delayed signal from the delay line through an AND gate, FIG. 4H shows a Q output signal g from the flip-flop 21, FIG. 4I shows a Q output signal h from the flip-flop 21, FIG. 4J shows an output signal k from NAND gate 23, FIG. 4K shows an output signal l from NAND gate 25, and FIG. 4L shows a clock signal i from NAND gate 27.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 3 is a circuit diagram of the signal detector of a magnetic disk apparatus according to an embodiment of the present invention. For ease of understanding, the numerals used to specify the components of the prior art in FIG. 1 denote the identical or corresponding parts in FIG. 3.

Referring to FIG. 3, in accordance with the present invention, an output signal from a delay line 17 is supplied to an AND gate 45. This output signal m from the AND gate 45 is synchronized with an output signal e from an inverter 19, signal e being formed from the same source as signal m and both having undergone one gate delay.

An output signal b from comparator 13 feeds the delay line 17 through an inverter 15. A NAND gate 25 receives an output signal f from comparator 11, an output signal g from the flip-flop 21 and signal m (previously described). According to the present invention, the output signal e from the inverter 19 which is synchronized with signal m, is supplied to the "D" input of flip flop 21 and to a NAND gate 23. The NAND gate 23 receives a Q output signal d from the comparator 11, a Q output signal h from the flip-flop 21, and signal e.

The operation of the signal detector having the configuration described above will be described with reference to FIGS. 4A through 4L. The read signal (analog voltage signal) a is produced by the magnetic head 1 and is supplied to the comparator 13 through a pre-amp 3 and an LPF 5. The comparator 13 generates the pulse signal b (FIG. 4B) which rises when the read signal a (FIG. 4A) exceeds a predetermined voltage level TH+ and which falls when the read signal a is less than a predetermined voltage level TH-. The pulse signal b is inverted by the inverter 15 and is delayed by the delay line 17 for a predetermined delay time. This scenario of events is similar to the prior art.

In accordance with the invention, the delayed signal is also supplied to an AND gate 45 and inverter 19. The inverted output signal e from the inverter 19 is supplied to the data input terminal D of the D flip-flop 21 and to NAND gate 23.

The read signal a from the magnetic head 1 is supplied as the differential signal c to the comparator 11, through the pre-amp 3, the LPF 5 and the differentiator 7. As a result, the comparator 11 generates pulse signals d (FIG. 4D) and f (FIG. 4E), which rise and fall in response to the zero-crossing point of the differential signal c, respectively. Pulse signal f is an inverted signal of pulse signal d. The differential signal c is an analog signal having zero-crossing points at the positive and negative peaks of the read signal a and is delayed for a predetermined time.

The differential signal c approaches the zero-crossing points when the slope of the read signal a comes close to zero. Because the zero-crossing points indicate the peaks of the read signal a, the comparator 11 outputs an undesirable (and incorrect) pulse, PX, at those points. Naturally, the pulse signals d, f containing the pulse PX (as shown in FIGS. 4D and 4E) are respectively supplied to the NAND gates 23, 25.

When pulse signals d and f are set at logic levels "1" and "0", respectively, signals m and e are set at logic levels "0" and "1", respectively, and signals g and h are set at logic levels "0" and "1", respectively. The output signal k from NAND gate 23 will then assume a logic level "0". Therefore, the output signal from NAND gate 27 will be forced to logic level "1", irrespective of the logic level of the output signal l from NAND gate 25. This state occurs at, for example, time interval t2 of FIGS. 4D-4J.

Next, assume that pulse signals d and f go to logic levels "0" and "1", respectively; that the flip-flop 21 receives signal e, in response to signal r (which corresponds to signal i of the prior art); and thus output signals g and h go to logic levels "1" and "0", respectively. Under such conditions, when signals e and m are set at logic levels "1" and "0", as shown in FIGS. 4F and 4G, respectively, the output signals k, l shown in FIGS. 4K and 4J (from NAND gates 23 and 25) will both assume the logic level "1" state. Therefore, the output signal r from NAND gate 27 is set at logic level "0", as shown in FIG. 4L. In this case, even if pulse signals d and f should assume logic levels "1" and "0", due to the undesirable pulses Px, the output signals k, l from the NAND gates are kept at logic level " 1".

As is clear from FIGS. 4D through 4I, only when signal d falls within the window t.sub.eh of a signal obtained by ANDing signals e and h, is it detected that signal d truly falls. Similarly, only when signal f falls within the window t.sub.gm of a signal obtained by ANDing signals g and m, is it detected that signal f truly falls.

As shown in FIG. 4D, even if jitter Px occurs in signal d during a period excluding window t.sub.eh, the logic level of signal r will not change. Similarly, as shown in FIG. 4E, even if jitter Px occurs in signal f during a period excluding window t.sub.gm, the logic level of signal i will not change. This means that the signal r shows only the peaks of the read signal a. Accordingly, unlike the above-discussed prior art, the flip-flop 21 has no race condition.

When the signal r (on which solely the peaks of the read signal a appear accurately) alone is used as a clock for the flip-flop 21, prevention of the race condition requires that the pulse width of the signal r be wider than a specific value tw. Such a width may be attained by selecting the time to be delayed by the delay line 17. The pulse width t2 shown in FIGS. 4D and E is controlled in the following manner:

t2>t1+tw,

where t1 is the time interval between the moment when the threshold level (TH+) of the comparator 13 crosses the read signal a and the moment when the threshold level has reached the peak of the read signal a; tW being the pulse width required for the flip-flop 21. Pulse width tW is shorter than pulse width t3.

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