A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output from the array. Single-bit data-in and data-out terminals for the device are coupled to the 4-bit array input/output in a sequential mode. The row and column addresses are latched when RAS and CAS drop, and the latched address includes the address of the starting bit within the 4-bit sequence for serial I/O. The other three bits follow as CAS is cycled. This starting address is used to set a bit in a 4-bit ring counter, which is then used to cycle through the sequence. To reduce power dissipation, the inverter stages of the ring counter are operated by pulsed clocks generated from the asynchronous memory control clocks received from the CPU.

In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.

In the semiconductor memory device havig a nibble mode function, memory cell arrays are divided into two groups of first and second cell blocks. Data bus lines are provided separately to each of the first and second cell blocks. Sense amplifiers are provided separately to each of the data bus lines. A column decoder, for connecting between bit lines, is provided in the memory cell array and corresponding data bus lines based on address signals and gate signals in a selection state. A switching circuit is provided for switching between sense amplifiers belonging to the first cell block and sense amplifiers belonging to the second cell block and for connecting these sense amplifiers to output buffers. A clock signal generating circuit is provided for generating the gate signals. The gate signals are generated in such a way that each gate signal is raised in response to a leading edge of a column address strobe signal and is allowed to fall in response to a trailing edge of the column address strobe signal in the nibble mode.

An improved DRAM having a plurality of main amplifiers for amplifying and storing signals read out to a plurality of common data lines in accordance with an internal address signal; a main amplifier control circuit for outputting the outputs of the main amplifiers sequentially in synchronism with changes in a column address strobe signal; an address counter for performing an addressing operation midway in the sequential reading operations of the plural main amplifiers; and a column selecting circuit for switching column switches in accordance with the address counter to cause data to be read out continuously at a high speed by extending a nibble mode.

In an integrated circuit random access memory internally a xn (n>1) organization is realized, that externally translates to a x1 organization. The n data bits read in parallel are successively and selectively activated and after multiplexing buffered in sequence. Upon buffering but not yet outputting the last data bit of a read address, the next read address may be applied. In this way a multi-address page mode or cross address nibble mode is realized. For writing, a resettable data input delay buffer maintains sufficient margin for both Tdh and Tdv in that any old data is deactivated before new data appears. In this way an equalization pulse no longer is required.