An apparatus for time aligning data acquired by one test instrument with corresponding data acquired by another test instrument is disclosed. A set of binary codes, representative of a set of instructions executed by a microprocessor disposed within a user's prototype circuit, are acquired by said one test instrument. With the acquisition of each of said binary codes, a count is developed in a counter indicative of each said acquisition. A multitude of binary data is acquired, independently of the acquisition of the set of binary codes, by said another test instrument, the multitude of binary data being representative of the functions performed by a set of components present within said user's prototype circuit. The binary codes acquired by said one test instrument and the binary data acquired by said another test instrument each have associated therewith a count developed from said counter. A mini-computer receives the binary codes acquired by said one test instrument, the binary data acquired by said another test instrument, and the counts corresponding thereto. The mini-computer time-aligns the binary data acquired by said another test instrument with the binary codes acquired by said one test instrument, using the counts associated therewith. A display of the time-aligned data is developed on a display device. As a result, when an instruction is executed by the microprocessor of the user's prototype circuit, using said display, it is possible to easily analyze the activity which took place among the components present within the user's prototype circuit as a result of the execution of said instruction by said microprocessor.
Logic output data of a plurality of channels simultaneously obtained from a circuit under test are sequentially input in a memory, and after inputting a predetermined amount of such data, they are compared with corresponding expected values. The input data are divided into blocks, each including a plurality of data. Whether a mismatch is present in the comparison results for each block is indicated by a respective block element, and such block elements are displayed in a predetermined arrangement. It is also possible to provide a conventional list display including the input timing corresponding to the comparison results in which a mismatch is present.
A guide probe test system for isolating faults in PC boards performs a "variable time domain" analysis by comparing probed data with stored reference data of waveforms of a known good UUT (unit under test) that are augmented by (1) insertion of shift coefficients to compensate for non-synchronization of the probed data with a start event, and (2) insertion of jitter coefficients to compensate for timing variations in the probed data due to allowable component propagation delay tolerances and/or an asynchronous clock. The insertion of the shift and jitter coefficients creates failure ranges within which mismatches of the probed data with the reference data are treated as possible rather than absolute failures. The UUT is partitioned into measurement sets containing nodes with common stimulus and synchronization to allow the analysis to break feedback loops and isolate faulty components. Use of the analysis is disabled when tracking faults across a measurement set and is re-enabled for further probing within a new measurement set. Insertion of shift and jitter coefficients into the stored reference waveform data for each node to produce failure ranges for each transition is accomplished by storing waveform data for that node from a good UUT, and determining the number of clock pulses by which transitions of that waveform may vary for multiple probings of that node, and by probing the corresponding nodes of multiple known good UUTs to determine the number of clock pulses by which each transition of that waveform may vary due to board-to-board variations. The failure ranges are fed to a probabilistic search routine that controls guided probing of the UUT. The system accomplishes at-speed fault isolation of UUTs containing multiple non-synchronized time bases.
The maintenance port system includes a maintenance unit, user prom, an available CRT terminal, and a prom software development package. This system accepts parametric definitions for an automatic panel as defined by the designer, and formats the panel data for display and modification on a CRT (cathode ray tube) terminal. Because the system controls the formats, standard display and modification procedures are then used for transmitting and receiving parameters and are the same from panel to panel.
A logic analyzer including at least a sampling system for sampling input data with a sampling clock signal comprises a condition decision circuit having inputs supplied with the input data and an internal clock signal for producing a conditioning signal in dependence on the input data in synchronism with the internal clock signal, a clock detection circuit for deciding whether the sampling clock signal makes appearance within a predetermined period of the internal clock signal to produce a signal representative of the result of the decision, and a control circuit having inputs supplied with the conditioning signal and the signal representative of said result for producing a trigger signal corresponding to the conditioning signal in dependence on the signal representative of the result of decision.
A tester-verifier apparatus operates to select a single one of a plurality of system clocks to verify that the clock width falls between accepted parameters. Secondarily, the apparatus selects representative clock signals for comparison with a reference clock to verify that the skew falls within accepted parameters. Additionally the apparatus can measure the exact time value of any pulse width or skew relationship to within 500 picoseconds (10.sup.-12). Any selected system clock signal is split into two channels, one of which has a controlled delay time programmed by a microprocessor to develop minimum and maximum pulse parameters against which the selected clock signal is logically compared to see if the parameters are satisfied.
