System for printed circuit board defect detection

What is claimed is:

1. Apparatus for determining defects in patterned images of lines and spaces of predetermined line width and spacing sizes comprising:

(a) an array of detectors for forming pixels consisting of a plurality of electronic bit signals corresponding to the image viewed by said detectors;

(b) memory apparatus for receiving said pixels sequentially by pixel and by line of said array and forming said pixels in a bit matrix of points in proper image orientation, all of such points being available for sampling;

(c) point selection means for sampling certain of the points of said bit matrix to form a set of defect detection points which set of points depends upon which defect is being detected;

(d) logic means for applying logical conditions to said defect detection points based on localized predetermined pattern rules to determine if defects in said patterned images are present;

(e) size selection means for selecting different sizes for the set of defect detection points for sampling depending on the predetermined line width or spacing sizes of the patterned image;

(f) indicating means for indicating the presence of such defects;

(g) said selection means including means for

(i) sampling "M" number of points of said bit matrix to form a first ring shaped pattern, the diameter D of which corresponds to the size of the minimum line width;

(ii) and sampling "L" number of bit matrix points to form a second ring shaped pattern concentric to said first ring shaped pattern;

(h) enable means for determining the number of said points on said inner ring in a first logic state indicating viewing of a line; and

(i) defect detection means for determining the number of consecutive points on said outer ring that are in an opposite logic state to said first logic state.

2. The apparatus of claim 1 including means to indicate a defect if all points on said inner ring are in said first logic state and more than about 70% of consecutive points on said outer ring are in an opposite logic state.

3. The apparatus of claim 1 in which the number of points on said outer ring are 18 and including means to determine the number of consecutive points on said outer ring which are in an oppesite logic state to the logic state of all points on the inner ring and to indicate a defect if the number is 13 or more.

4. The apparatus of claim 1 including size selection means for selecting one of a plurality of inner ring sizes and one of a plurality of outer ring sizes in accordance with the size of the predetermined line width.

5. The apparatus of claim 1 wherein "M" is a number from and including 6 to 8 and "L" is 18.

6. The apparatus of claim 5 in which an unterminated line defect is indicated when all points on said inner ring are in said first logic state and 13 or more consecutive points on said outer ring are in an opposite logic state to said first logic state.

7. Apparatus for determining defects in patterned images of lines and spaces of predetermined line width and spacing sizes comprising:

(a) an array of detectors for forming pixels consisting of a plurality of electronic bit signals corresponding to the image viewed by said detectors;

(b) memory apparatus for receiving said pixels sequentially by pixel and by line of said array and forming said pixels in an a bit matrix of points in proper image orientation, all of such points being available for sampling;

(c) point selection means for sampling certain of the points of said bit matrix to form a set of defect detection points which pattern depends upon the defect being detected;

(d) logic means for applying logical conditions based on localized predetermined pattern rules to determine if defects in said patterned images are present;

(e) size selection means for selecting different sizes of the set of defect detection points for sampling depending on the predetermined line width and spacing sizes of the patterned image;

(f) indicating means for indicating the presence of such defects;

(g) and wherein said selection means comprises:

(i) means for sampling "M" number of points of said matrix to form a first inner ring of points; and

(ii) means for sampling "L" number of points of said matrix to form an outer ring of points concentric to said inner ring; and wherein

(h) the logic means includes means for comparing the logic state of selected opposite pairs of points on said outer ring to determine if the logic state of each pair is identical.

8. The apparatus of claim 7 in which "L" and "M" is 36.

9. The apparatus of claim 7 in which a defect is indicated if:

(i) the logic state of less than three such opposite pairs of points are not identical; and

(ii) all points on said inner ring are in a logic state corresponding to a line image; and

(iii) less than a predetermined number "X" of the points on said outer ring are in the same logic state as the points on said inner ring.

10. The apparatus of claim 7 including means for coupling said opposite pairs of points to Exclusive OR gates to determine if a mismatch in logic states is present.

11. The apparatus of claim 9 including means for adding the number of opposite pairs of points which are mismatched and providing a 5 bit binary number corresponding thereto and using the two least significant bits of said 5 bits to determine if the number of mismatches is 3 or more.

12. The apparatus of claim 9 wherein X is equal to or less than 16.

13. Apparatus for determining defects in patterned images of lines and spaces of predetermined line width and spacing sizes comprising:

(a) an array of detectors for forming pixels consisting of a plurality of electronic bit signals corresponding to the image viewed by said detectors;

(b) memory apparatus of receiving said pixels sequentially by pixel and by line of said array and forming said pixels in a bit matrix of points in proper image orientation, all of such points being available for sampling;

(c) point selection means for sampling certain of the points of said bit matrix to form a set of defect detection points depending upon the defect to be detected;

(d) logic means for applying logical condiitions based on localized predetermined pattern rules to determine if defects in said patterned images are present;

(e) size selection means for selecting different set sizes of defect detection points for sampling depending on the predetermined line width and spacing sizes of the patterned image;

(f) indicating means for indicating the presence of such defects; and wherein

(g) said selection means includes means for sampling "M" number of points of said bit matrix to form "L" number of radii of points emenating from a center and spaced from one another; and wherein

(h) said logic means including means for comparing the logic state of selected pairs of points, A and B, on opposite radii with selected pairs of points, C and D, on radii orthagonal to the radii on which said A and B bit points lie to determine if the logical condition A B C D is satisfied.

14. The apparatus of claim 13 including means for selecting the "M" number of points in accordance with the known line width and spacing.

15. The apparatus of claim 13 wherein the A and B pairs of points are selected to correspond to the known line to line spacing and the C and D points to the known line width.

16. The apparatus of claim 13 wherein "L" is 18.

17. Apparatus for determining defects in patterned images of lines and spaces of predetermined line width and spacing sizes comprising:

(a) an array of detectors for forming pixels consisting of a plurality of electronic bit signals corresponding to the image viewed by said detectors;

(b) memory apparatus for receiving said pixels sequentially by pixel and by line of said array and forming said pixels in a bit matrix of points in proper image orientation, all of such points being available for sampling;

(c) point selection means for sampling certain of the points of said bit matrix to form a set of defect detection points depending upon the defect being tested for;

(d) logic means for applying logical conditions to said defect detection points based on localized predetermined pattern rules to determine if defects in said patterned images are present;

(e) size selection means for selecting different set sizes of defect detection points for sampling depending on the predetermined line width and spacing sizes of the patterned image; and

(f) indicating means for indicating the presence of such defects.

18. The apparatus of claim 17 in which the line images are indicated by a pixel signal of one logic state and non-line images by a pixel signal of the opposite logic state.

19. The apparatus of claim 18 in which the existence of non-lines on lines or the converse is determined by:

(a) said point selection means sampling "M" number of points on said bit matrix to form an X-shaped pattern of points and an "L" number of points on said bit matrix to form a second shaped pattern of points around said X-shaped pattern; and

(b) logic means for comparing the logic state of the points on each X-shaped pattern with those of the second-shaped pattern to determine if the states are the same or different.

20. The apparatus of claim 17 wherein the number of points capable of being selected is 1000 or more.

21. The apparatus of claim 17 in which an analog pixel signal from an array is converted to a binary digital signal of one of two logical states in a threshold circuit.

22. Apparatus for determining defects in patterned images of lines and spaces of predetermined line width and spacing sizes comprising:

(a) an array of detectors for forming pixels consisting of a plurality of electronic bit signals corresponding to the image viewed by said detectors;

(b) memory apparatus for receiving said pixels sequentially by pixel and by line of said array and forming said pixels in a bit matrix of points in proper image orientation, all of such points being available for sampling;

(c) logic means for applying logical conditions based on localized predetermined pattern rules to determine if defects in said patterned images are present;

(d) point and size selection means for sampling "M" number of points on said bit matrix to form an X-shaped pattern of points and "L" number of points on said bit matrix to form a second pattern of points around said X-shaped pattern and for varying the size of the second pattern of points in accordance with the known size of the lines and spaces; and

(e) wherein said logic means compares the logic state of the points on each X-shaped pattern with those of the second pattern to determine if the states are the same or different.

23. The apparatus of claim 22 wherein M is 5 or more and L is 8 or more.

24. A method for determining defects in patterned images of lines and spaces of predetermined line width and spacing sizes comprising the steps of:

(a) arranging an array of detectors to form pixels consisting of a plurality of electronic bit signals corresponding to a patterned image viewed by said detectors;

(b) receiving said pixels sequentially by pixel and by line of said array and forming said pixels in a bit matrix of points in proper image orientation, such that all of such points are available for sampling;

(c) sampling certain of the points of said bit matrix to form a set of defect detection points depending upon the defect being tested for;

(d) applying logical conditions to said defect detection points based on localized predetermined pattern rules to determine if defects in said patterned images are present;

(e) selecting different set sizes of defect detection points for sampling depending on the predetermined line width and spacing sizes of the patterned image; and

(f) indicating the presence of such defects.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to an arrangement for optically inspecting patterned images for defects, and more particularly pertains to an unique optical sensor system for examining a printed wiring board for any defects thereon.

2. Discussion of the Prior Art

The detection of defective printed wire circuit boards presents a rather complex problem, the solution of which would yield significant and immediate economic benefits. This quality control problem extends from the fabrication of conventional printed wiring boards to the high resolution masks employed in photolithography for very large scale integrated (VLSI) circuits. A typical modern printed circuit board manufacturing facility is an interesting study in contrasts. Most of the fabrication operations such as printing, plating, drilling, routing, etc., are heavily automated. But, inspection of the completed boards is frequently performed manually by inspectors with magnifiers who visually check the boards and artwork for flaws. It turns out that in many cases, the inspection of a printed circuit board is as expensive as its manufacture because of the labor intensive activity involved therein.

The inspection of the inner layers of multilayer printed circuit boards is particularly important for a number of reasons. They are extremely difficult to inspect because of the small line width and the density and complexity of the patterns thereon. Moreover, a complete one hundred percent visual inspection of inner layer boards is usually required because of the expense of rejecting a completed laminated board at the final electrical test.

Automated inspection of printed circuit boards would appear to be particularly applicable to multilayer boards as they are often computer designed and plotter generated, which implies a uniformity of lines and spaces as well as an absence of lettering and extraneous markings in the circuitry area. Initial investigations into automated inspection of printed wire boards included consideration of image comparison techniques using either a master printed circuit board, the artwork, or a computer stored map. However, this concept was not pursued as troublesome problems were encountered. Since the instantaneous area of the scanned image, or pixel-under-test, must match the corresponding area of the master, exact alignment is necessary at every point on the board. Shrinking or swelling of the board due to changes in temperature or humidity would have to be compensated for, as would the normal and perfectly acceptable variations in the widths of the lines and spaces of the pattern. As a result of these problems, it became evident that the complexities inherent in the mechanization of this technique would make the finished instrument only marginally economical as a replacement for human inspectors.

Similar problems exist with a comparison of optical Fourier transforms. In this case, if a line at the edge of the scanned area is included in one field of view and omitted from the other as a result of scan misalignment, the Fourier energy distributions will not match.

Bentley in "the inspectron: an automated optical printed circuit board (PCB) inspector", SPIE Vol. 201, Optical Pattern Recognition (1979), p 37-47, discloses an automated printed wire circuit board inspection machine which mechanically scans a hardwired distance-measuring sensor array of photodetectors over the circuit board and utilizes logical decisions on the image pattern of the illuminated and nonilluminated detector to detect defective circuit boards.

Restrick in "An Automatic Printed Circuit Inspection System" SPIE Vol 116 Solid State Imaging Devices (1977) describes a system for printed circuit inspection which does not require mechanical scanning of the sensor array over the circuit board. Instead, optical sensors scan a swath of a board as the sample board moves by on a support table.

Three sensing units each scanning a 1.6 inch wide swath of the moving sample are used. A lens associated with each sensing unit images a moving sample onto a 1728 element linear solid-state optical sensor. The sensor is positioned perpendicular to the direction of motion so that the sample is scanned mechanically in one direction and electronically by the sensor in the other. The portion of the object being imaged onto the array is illuminated from each side by miniature tungsten-halogen lamps and cylindrical lenses.

Buffers are mounted close to the sensing array to relay the driving waveforms to it. The array output is amplified and quantized to binary levels-indicating the presence of one of two materials. The quantization is made by comparing the array output with threshold values. To correct for spatial nonuniformities in the illumination, optics, and sensor, each sensor has its own threshold value. As each successive element is read out, an eight bit digital threshold value, retrieved from a memory is converted to an analog value and substracted from it. The threshold values are created automatically by placing a uniform standard reflectance target in the optical system prior to inspection.

Shift registers store individual line scans. A special purpose processor consisting of registers to manipulate and temporarily store the data, and digital logic to implement the error detecting algorithm is required for each sensing unit. Six consecutive scan lines are stored by daisy chaining six 2048-bit shift registers. The array scans in the y direction and the object is scanned mechanically in the x direction. The output of each register is a bit stream representing successive y positions for fixed x. Six consecutive outputs from each of the six shift registers are stored in single bit registers. Simple combinational logic applies line width/line spacing criteria to the contents of the registers. With each clock pulse a new 6.times.6 area is stored in the shift registers and the error criteria applied.

As errors are detected, position sensing unit identification and error type (clearance or width) information are stored on a stack-organized memory. A microprocessor retrieves this information from the stack and stores it along with the table position. At the end of the inspection operation, the information is used to calculate x and y coordinates relative to the circuit being inspected, and the error locations are printed out.

SUMMARY OF THE INVENTION

It is a primary object of the present invention to provide an arrangement for inspecting a printed wiring circuit board based upon logical decisions resulting from an examination of binary image patterns representing the circuit board.

A further object of the subject invention is the provision of an arrangement of the aforementioned type which can be implemented by a relatively simple array of sensors.

In a preferred embodiment of the invention, the video signals from each scanned line of a photodetector array, after thresholding and digitizing, are accumulated in a plurality of shift registers, specifically in 32 shift registers each 32 bits in length. A moving "window" or "matrix" of "N" by "N" matrix points (in this case 32.times.32or 1024 bit output points) is thus made available in the instantaneous contents of the shift registers. Each point in this matrix is in one of two possible logical states or polarities, that is, either an ON or OFF (a ONE or ZERO logic condition) depending on the instantaneous image viewed by a corresponding photodetector element in the array.

Any of the 1024 points in the matrix can be selected or addressed. The contents thereof can be selected and a variety of logical principles applied thereto to determine if the image available in the 32.times.32bit matrix window violates logical printed circuit board principles. Specifically, in the preferred embodiment defects can be detected, such as (a) the presence of unterminated lines, (b) failure to meet minimum conductor width and spacing specifications, (c) the presence of holes in small areas of conductors or conductors in small areas of insulators, or (d) the presence of conductors having line widths in excess of specification. Moreover, a point select capability permits the system to apply the defect detection logic to a plurality of line width and spacing sizes. For example, in a preferred embodiment of the system conductor widths and spaces of 0.003 inches to 0.0105 inches can be accommodated in increments of 0.0005 inches.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing objects and advantages of the present invention for an optical sensor for printed circuit board defect detection may be more readily understood by one skilled in the art with reference being had to the following detailed description of several preferred embodiments thereof, taken in conjunction with the accompanying drawings wherein like elements are designated by identical reference numerals throughout the several views, and in which:

FIG. 1 is a schematic block diagram of a further embodiment of the invention capable of determining defects for a plurality of printed wire board conductor widths and spaces.

FIG. 2 is a schematic illustration of a portion of the electro-optics of FIG. 1.

FIG. 3 is a schematic illustration of the threshold circuitry of the embodiment of FIG. 1.

FIG. 4 is a schematic illustration of the matrix forming memory 50 and matrix 52 circuits of FIG. 1.

FIGS. 5A and 5B taken together form a schematic diagram of the point selection circuit of FIG. 1.

FIG. 6 is a representation of the sensor pattern arrangement for defect detection of unterminated conductors (Sensor A).

FIG. 7 shows the logic circuitry for the Sensor A enable ring.

FIG. 8 shows the Sensor B (minimum line width and spacing) point selection circuit.

FIG. 9 is a representation of the pattern for the Sensor B ring.

FIG. 10 is a representation of the sensor pattern for Sensor C circuit (small area defect).

FIG. 11 shows the Sensor C (small area defect) error detection circuit.

FIG. 12 shows the Sensor B (minimum line width and spacing) error detection circuit.

FIG. 13 shows the Sensor D (fat line defect) error detection circuit.

FIGS. 14A-D show details of the sensor pattern arrangement for Sensor D.

FIG. 15 shows the Sensor A (unterminated line) defect detection logic circuit.

DETAILED DESCRIPTION OF THE DRAWINGS

The logic utilized by the present invention is based upon given inherent characteristics of a correctly produced printed wire circuit board, including the following:

1. All circuit lines end in pads, and any line that does not is almost certainly broken, and can be considered an error.

2. All circuit lines have a specified minimum line width. There is also a minimum line spacing which is usually but not necessarily identical with the minimum line width. Therefore, if a feature is found on a circuit board which has any dimension smaller than this minimum, it must be an error, either an illegal width line, an illegal width space, a piece of spurious copper, or a void in a copper area.

3. Any copper feature the smallest dimension of which is much larger than a standard line but smaller than a pad is an error, either a broken pad or a spurious copper blob.

New high density or fine line printed wiring boards are characterized by the following tolerances in conductor width, spacing and pad size:

______________________________________ Nominal, (in.) Minimum, (in.) ______________________________________ conductor widths 0.008 0.006 conductor-conductor 0.008 0.006 spacing pad diameter 0.055 0.050 ______________________________________

The present invention is designed to detect defects on a printed-wiring circuit board with an array of concentric rings of optical sensors. The sensors are binary in that they register a ONE if looking at conductive material, and a ZERO otherwise. With a typical printed circuit board, each detector is energized to an "on" or one state by reflection from a pixel (the increment of area which the detector is examining) formed of bright copper, and each detector is de-energized to an "off" or ZERO state by reflection from a pixel formed of the matte substrate. Furthermore, negatives can be examined by a simple inversion of the state of each pixel. Moreover, the threshold determination for each detector between a ONE state and a ZERO state could be a dynamic determination wherein the output of each detector or plurality of detectors is evaluated and weighed in making the threshold determination. The detectors are arranged such that certain patterns of ONE's and ZERO's imply a defective area on the circuit board.

A relatively small electrical moving "window" or image is provided as the board is scanned by the CCD arrays. Selected points on this window are then addressed and logic applied to test for defects in a continuous manner. Such a system will now be described in connection with FIGS. 1-14.

Referring to FIG. 1, there is shown in schematic form a printed wiring board (PWB) inspection system. PWB's 10 are placed on a transport 12, such as a conveyor belt, and pass between a pair of illumination lamps 14 and 16 disposed on either side of transport 12. It is important that the PWB 10 be accurately registered on the transport 12 so that PWB defects can be verified on a companion machine (not shown) containing a computer-controlled X-Y table to position detected defects in the field of view of a TV camera display system. Registration may be accomplished using tooling holes on the PWB 10 or the edges of the board. Solenoids 34 and 32 used for registration and clamping, respectively, of the PWB are energized by signals from scanner command and status unit 40.

Unit 40 receives transport position signals from transport control unit 30 which is fed by encoder 28 and tachometer 26. Transport drive motor is driven by transport control unit 30 in response to command and clock signals from status unit 40.

Lamps 14 and 16 may comprise linear tungstenhalogen lamps energized by lamp supply voltages from power supplies 36 and 38. The lower lamp 16 is used for imaging artwork by transmitted light through a slit not shown in transport 12. The same principles discussed herein with respect to PWB inspection are used in the transmissive mode. Therefore, it will be understood that the invention is not limited to PWB inspection by reflective light, but is equally applicable to inspection of light transmissive media.

It should be understood that system control calibration and synchronization (clock) signals are generated by computer 44 which may, for example, comprise a DEC PDP-11. These signals are coupled to appropriate portions of the system via calibration bus 44c, test bus 44b, defect report bus 44f, command and status cable 44dand system clock cable 44e.

Light source 14 and beam splitter 18 are preferably included in a light integrating cavity 7. Cavity 17 functions as an isotropic light producing means. Lamp or light source 14 produces light which passes through a light diffuser (not shown) and which strikes interior wall portions of the light integrating cavity 17 which are preferably coated with a flat white paint. Lens 20 and CCD 22 are positioned along optical viewing axis 20a and a skewed beam-splitter 18 is positioned at an angle with respect to the viewing axis. Preferably, the beam-splitter has a light transmission factor of about 10%. Light reflected, for example, by a wall portion of cavity 17, and striking the surface of beam-splitter 18, is re-reflected along the optical axis toward the PWB board being viewed through a slit or aperture 11 (not shown) in the bottom of cavity 17.

As light is reflected a number of times within integrating cavit