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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a controller for a fixed disk drive and
more particularly to a fixed disk drive controller for use in a word
processing system.
2. Description of the Prior Art
It is desirable in word processing equipment to have a fixed disk drive to
store data and programs.
Many word processing systems currently available consist of a keyboard, a
printer, a display and a floppy disk drive, all controlled by one or more
microprocessors. Floppy disk drives have been shown to be cost effective
means by which programs and data can be stored and accessed on demand by
the operator. Compared to other forms of data storage, such as magnetic
tape cassettes, magnetic cards and punched paper tape, floppy disks allow
the user to access more information and to access the information faster.
It has been found, however, that for larger systems requiring more data
manipulation and formatting, the floppy disk system is inadequate.
Resource sharing and time sharing data or word processing systems, for
example, generally require a larger data base and shorter access time than
do stand alone systems. Moreover, sophisticated operations such as merging
of files, sorting of data within files, and dictionary capabilities often
require more memory space and shorter cycle times to be performed
efficiently in real time. Finally, for complex data handling procedures,
increased reliability is also required.
The relative advantages of floppy disks over magnetic tape, cards and paper
tape unfortunately dissolve in the aforementioned environments. The
solution to the problems inherent in floppy disk systems can be found by
using one or more hard or fixed disks in conjunction with or in lieu of
floppy disks.
As word processing systems become more sophisticated, the storage capacity
of their mass memory mediums must increase and the speed at which data is
stored and retrieved must decrease. For these reasons, one or more
flexible (floppy) disks may not be adequate to access a great amount of
data in a relatively short time, even if the floppy disks are dual-sided,
double density.
A rigid or fixed disk, on the other hand, has a larger storage capacity and
the disk drive associated with it is generally capable of rotating it at a
greater velocity. It is therefore advantageous to adapt such a rigid disk
for use with a word processing system. A rigid disk, and in particular a
Winchester disk, is coated on both sides with a magnetic medium, so that
two surfaces per disk are available for the storage of data. Each
Winchester read/write head has three rails, or raised surfaces. The
trailing end of the middle rail holds a magnetic core with wire coiled
around for writing and reading the data. The two outer rails govern the
flow of air. The force that results is sufficient to support a weight of
10 grams at a height of half a micrometer above the disk. The disks and
the head assemblies in such a memory are sealed in a small chamber in
which the air is continuously recirculated an filtered to exclude any dust
particles larger than 0.3 micrometer in diameter.
The quantity of data that can be stored on a disk depends on how much of
its surface area is magnetized for the storage of a bit. The width of a
magnetized region, or equivalently the width of a data track, is affected
by limitations on both the head and the disk. The width of the center rail
of a Winchester head is approximately 20 micrometers, which corresponds to
a track density on the disk of about 1,000 per inch of the radius. On a
floppy disk however, the track density is only 48 tracks per inch for
single density disks (96 tracks per inch for double density disks).
In high-performance memories the one of the surfaces of a disk is devoted
to patterns of bits that continuously yield information on the position of
the head. Any deviation from the proper position causes the generation of
a signal in the head that actuates a motor for repositioning. Such
patterns of bits may be embedded within the stored data itself.
The number of bits that can be written along a track also is affected by
limitations on both the head and the disk. As a result of all these
constraints the number of reversals in magnetism along a data track in a
device that records digital data by magnetic saturation and employs a
Winchester head is about 10,000 per inch. The quantity of data stored
ranges from about 20 million bits for one surface of a floppy disk to
billions of bits for high-performance rigid disks.
The rate at which bits are written or read along a track is called the data
rate. It ranges from hundreds of thousands of bits per second for floppy
disk systems to 10 million bits per second for rigid disk systems. The
main reason for the difference is the fact that floppy disks must rotate
at lower speeds.
The configuration of disk drives and their associated controllers has
heretofore been a matter of connecting a CPU or processor to one or more
disk controllers and connecting one disk drive to each of the disk
controllers. A more elaborate system of daisy chaining disk drives, one of
which drives is connected to a disk interface and controller, is disclosed
in U.S. Pat. No. 4,064,561, issued to Jennings. In that system, two disk
interface and controller units are shown connected to a CPU. Each of the
disk interface and controller units controls up to four daisy chained disk
drives, each of which drives includes two disks, one fixed and the other
removable. Thus, a maximum of 16 disks can be incorporated in that system.
A system in which a fixed disk controller is connected to a floppy, or
removable disk controller provides a number of advantages in terms of
system efficiency and flexibility. One of the advantages is that the
system can be configured to operate satisfactorily in a minimum
configuration of a single floppy disk, but yet can be expanded to include
one or more fixed disks in addition to or in lieu of the floppy disk.
Thus, the advantage of such a piggy back system of fixed disk control over
the aforementioned daisy chained disk configuration is that one of the
fixed disk drives can be removed in the piggy back system with minimal
effort without significantly affecting system operation. A removal of one
of the daisy chained disk drives, on the other hand, obviously renders all
system drives connected to it down-stream inoperable.
SUMMARY OF THE INVENTION
The present invention permits a fixed disk drive to be incorporated in a
word processing system.
A system has been invented for allowing one or more fixed disk drives to be
used in a word or data processing system in addition to or in lieu of one
or more floppy disk drives. The fixed disk drive provides greater
flexibility in a word processing system by allowing larger programs and
more data to be stored and decreasing the time required to access
information so stored. Relatively complicated word processing operations
such as merging of files and sorting of items or records in a file can be
performed with fixed disks much more readily than could have been
performed previously with the use of floppy disks alone. Moreover, the
marked decrease in access time allows greater efficiency of time sharing
and resource sharing operations than systems heretofore available.
In accordance with the present invention, there is provided a word
processing system comprising a display for exhibiting alphanumeric
information, a first controller connected to the display for controlling
the exhibition of the alphanumeric information, a second controller for
controlling the transfer of information to and from a data storage device,
said second controller including random access memory having a direct
memory access port and further including a central processing unit, an
interprocessor communications means for providing a communications path
between said first and second controllers, and a fixed magnetic disk
controller for controlling the transfer of data to and from a fixed
magnetic disk, the fixed magnetic disk controller including a status
register operatively connected to the central processing unit and a direct
memory access control means for transferring data to and from the random
access memory of the second controller through its direct memory access
port.
In a preferred embodiment of the subject invention, the magnetic disk
controller responds to a preselected status signal set in the status
register by the CPU to read command data from the random access memory
through the direct memory access port and the fixed magnetic disk
controller further responds to the command data to transfer data between
the random access memory and the fixed magnetic disk in accordance with
the command data and without further control by the second controller.
BRIEF DESCRIPTION OF THE DRAWINGS
A complete understanding of the present invention may be obtained by
reference to the accompanying drawings, when taken in conjunction, with
the detailed description thereof and in which:
FIG. 1.is a block diagram of a typical word processing system configuration
embodying the present invention;
FIG. 2 is a flow chart representing system operations in accordance with
the present invention;
FIG. 3 is an interconnection diagram of FIGS. 3a and 3b which, taken
together, are a block diagram of the fixed disk controller in accordance
with the present invention;
FIG. 4 is an interconnection diagram of FIGS. 4a through 4c which, taken
together, are a schematic diagram of the data path sequencer of the
present invention;
FIG. 5a is a flow chart representing disk write and DMA read operations of
the data path sequencer in accordance with the present invention;
FIG. 5b is a flow chart representing disk read and DMA write operations of
the data path sequencer in accordance with the present invention;
FIG. 6 is an interconnection diagram of FIGS. 6a through 6f which, taken
together, are a schematic diagram of the hardware sequencer of the
present, invention;
FIGS. 7, 8 and 9 are interconnection diagrams of FIGS. 7a and 7b, 8a and 9a
and 9b respectively which, taken together, are a representation of the
disk sequencer write header format (FIGS. 7a and 7b), the disk sequencer
write command and write check ECC control functions (FIGS. 8a and 8b), and
the disk sequencer read command control functions (FIGS. 9a and 9b) of the
present invention;
FIG. 10 is an interconnection diagram of FIGS. 10a and 10b which, taken
together, are a chart of a disk format sequencer code in accordance with
the present invention;
FIG. 11 is an interconnection diagram of FIGS. 11a through 11d which, taken
together, are a schematic diagram of the data separator start logic and
disk clock with MFM read data of the present invention; and
FIG. 12 is an interconnection diagram of FIGS. 12a through 12f which, taken
together, are a schematic diagram of the MFM data encoder and the data
separator in accordance with the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to FIG. 1, the minimum configuration for a fixed disk
controller includes a keyboard 110 operatively connected to a CRT
processor 112 over an interprocessor communications (IPC) bus 114 to a
floppy disk processor 116. A rigid disk controller 118, is connected to
the floppy disk processor 116. Up to four rigid disk drives, shown
generally at reference numeral 120, can be connected to the rigid disk
controller 118. The disk drives 120 may be 51/4", 8" or 14" Winchester
technology drives, such as Model No. SA1004 or other model numbers in the
SA1000 series manufactured by Shugart Associates, Inc. or Model No. Q2040
or other model numbers in the Q2000 series manufactured by Quantum, Inc.
The rigid disk controller 118, may be designed to fit in an encasement
commonly called a floor module. The floor module electronics of the
present invention consists of the CRT processor 112, the floppy disk
processor 116 and the rigid disk controller 118 and is shown generally in
phantom as reference numeral 122. A local network interface circuit board,
not shown, can also be included in the floor module. The rigid disk
controller 118 controls the disk drives 120, which contain hard or fixed
disks, not shown, to provide the user with mass storage. These disks may
contain data files and records as well as correspondence, all of which are
generally grouped as data bases.
The disk drives 120 receive commands and instructions from an operator via
the keyboard 110 into the data or word processing system.
From the keyboard 110, commands are decoded and passed to the floppy disk
processor 116 by software. The floppy disk processor 116, in conjunction
with the software in the system, requests data transfers of the rigid disk
controller 118.
The rigid disk controller 118 is not a stand-alone controller in the
system. It must be used in conjunction with the floppy disk processor 116.
This is because the rigid disk controller 118 has no access to the IPC bus
114 or to the system bus, not shown.
Once the rigid disk controller 118 receives a data transfer or position
command, in the case of a data transfer request from the floppy disk
processor 116, the rigid disk controller 118 disconnects from the floppy
disk processor 116 until the command is executed. At the conclusion of a
read command, if no data errors are encountered, the rigid disk controller
118 passes to the floppy disk processor 116 an ending status, indicating
that the command has terminated. If an error occurs during a disk read
operation, the rigid disk controller 118 attempts to correct the error. If
the error is correctable, the data is corrected and transferred via direct
memory access (DMA) to a memory location in the floppy disk processor 116.
At the conclusion of that operation, the floppy disk processor 116 is
notified that the command has terminated.
In the case of a write command operation, the rigid disk controller 118
transfers a 256-byte block of data via DMA from the floppy disk processor
116 to the floppy disk processor onboard buffer. The requested sector
and/or track of the disk specified by the command is then accessed. The
256-byte block of data is then transferred to the requested drive 120, and
the floppy disk processor 116 is notified on completion of the operation.
If more than one block of data is desired, however, the floppy disk
processor 116 initially loads an area in its memory with all the data to
be transferred. The rigid disk controller 118 then transfers via a DMA
operation the first block of data before beginning data transfer to the
disk. Once the first block of data is successfully transferred, the data
transfer is initiated on the selected drive 120. In parallel with the
aforementioned operation, a fetch operation of the next data block is
performed from the floppy disk processor's memory. Accordingly, on
termination of the first data block transfer, the second data block is
available for transfer. This increases the throughput of the system.
A similar sequence occurs for read command operations. During a read
operation, the rigid disk controller 118 first reads one block of data
from the disk drive 120 before it initiates a DMA transfer to the memory
of the floppy disk processor 116. While the first data block is being
transferred to the floppy disk processor 116, the second data block is
fetched from the disk, and so on.
Referring now also to FIG. 2, a flow chart of system operations is shown.
Reference numerals for FIG. 2 beginning at number 130 and terminating at
number 146 refer to flow chart or programming steps.
In order for the rigid disk controller 118 (FIG. 1) to access data, an
operator initially makes a request at the keyboard, step 130 (FIG. 2).
This request is passed via software to the file system, step 132. The
software decodes the command and passes that decoded information to the
floppy disk processor 116, step 134.
The rigid disk controller 118 in an idle state executes a programming loop
on status, step 138. The status flag it seeks is called a COMMAND PACKET
AVAILABLE flag. In the absence of a command from the floppy disk processor
116, the rigid disk controller 118 remains in this tightly controlled
programming loop.
When the floppy disk processor 116 has a command available for the rigid
disk controller 118, it initializes the COMMAND PACKET AVAILABLE flag. The
rigid disk controller 118, on detecting the COMMAND PACKET AVAILABLE flag,
initializes the data path sequencer to fetch the command packet from the
floppy disk processor's memory, step 140. The data path sequencer, on
executing the command packet fetch instruction, step 142, passes a status
flag to the rigid disk controller 118. At that point, the rigid disk
controller 118 decodes and executes the command, step 144.
Once the rigid disk controller 118 has decoded the command, the actual
execution is done by the hardware format sequencer. On execution of the
command, the rigid disk controller 112 informs the floppy disk processor
116 that the command has completed successfully or has been rejected, step
146. After notifying the floppy disk processor 116 of the command status,
the rigid disk controller 118 returns to the programming control loop,
step 138, to seek the next command to be passed to it from the floppy disk
processor 116. The rigid disk controller 118 remains in this programming
loop until it receives a command from the floppy disk processor 116.
Referring now to FIG. 3, there is shown a more detailed block diagram of
the fixed or rigid disk controller in accordance with the present
invention. A floppy disk processor is provided at reference numeral 210.
Connected to the floppy disk processor 210 over data lines labelled HDD7-0
are transceivers 212, such as Model No. 8304B manufactured by Advanced
Micro Devices, Inc. (hereinafter AMD).
A communications bus 214 connects the transceiver 212 to registers and
other devices. A command register 216, such as Model No. 74LS374
manufactured by AMD, is connected to the communications bus 214. A direct
memory access (DMA) data in register 218, such as Model No. 74LS374
manufactured by AMD, is also connected to the communications bus 214. An
error register 220, such as Model No. 74LS244 manufactured by Texas
Instruments (hereinafter TI) is connected to the communications bus 214,
as in a status register 222, such as Model No. 74LS374 manufactured by TI.
Interrupt control logic, including Model Nos. 74LS74 and 74LS125, is
provided at reference numeral 224 and is also connected to the
communications bus 214. Finally, a DMA data out register 226, such as
Model No. 74LS374 manufactured by AMD, is also connected to the
communications bus 214.
Also connected to the floppy disk processor 210, over address lines
labelled HDAD0-7 is a transceiver 228, such as Model No. 74LS244
manufactured by AMD, which in turn is connected to an address decoder
circuit 230 including Model Nos. 74LS155, 74LS10, 74LS02 and 7425
manufactured by TI. DMA control circuitry 232 including Model Nos.
74LS123, 74LS74, 74LS244, 74LS32 and 74LS08 manufactured by TI is also
provided to interface with the floppy disk processor 210 over lines marked
direct memory access request (DMA REQ) and direct memory access
acknowledge (DMA ACK).
A microprocessor 234, such as Model No. 8085-A manufactured by the Intel
Corp. (hereinafter Intel), is provided to interface with the status
register 222. Connected to the microprocessor 234 are a 1K.times.8 byte
random access memory (RAM) 236, such as Model No. 2114 manufactured by
Intel, and a 4K programmable read only memory (PROM) 238, such as Model
No. 2716-1 manufactured by Intel. A data buffer such as Model No. 8304B
(not shown) and an addres latch, such as Model No. 74LS373 (not shown)
both manufactured by AMD, are located between the microprocessor 234 and
both memory devices 236 and 238. A microprocessor data bus 240 is provided
to interface the microprocessor 234 and memory devices 236 and 238 over a
data line to the command register 216 and to the status register 222.
Connected to the microprocessor 234 over address lines ADD7-0 is a control
function decoder circuit 242 including Model Nos. 74LS138 and 74LS02
manufactured by TI. A load command line is provided from the control
function decoder circuit 242 to a hardware format sequencer 244, which
consists of two devices such as Model No. 74LS138 manufactured by TI.
A DMA and RAM buffer control 246, such as Model Nos. 74LS138 and 74LS08
manufactured by TI, AMD, and the Signetics Corp. (hereinafter Signetics),
is connected to the data path sequencer 244 to provide DMA and RAM buffer
control.
Sequencer DMA request and DMA acknowledge lines are connected between the
buffer control 246 and the DMA controls 232. The buffer control 246 is
also connected to the DMA data out register 226 via a LOAD DMA DATA line,
and to the interrupt control 224 via a SEQUENCER INTERRUPT line. A line
from the buffer control 246, ENABLE DESERIALIZER DATA, is applied to a
deserializer data latch 247, such as a Model No. 74LS374. The output of
this deserializer data latch 247 is applied to the RAM data input
multiplexer 262. A LOAD DATA line is generated by the hardware format
sequencer 244 and applied to a serializer/deserializer 248, which consists
of two devices such as Model No. 74LS95 manufactured by Signetics.
Connected to this serializer/deserializer 248 is a non-return-to-zero
(NRZ) data multiplexer 250, such as Model No. 74LS51 manufactured by AMD.
A line is provided from the NRZ data multiplexer 250 to an error
correcting code (ECC) generator 252 manufactured by TI.
ECC Generator Operation
The ECC generator operation 252 is used during a write operation to
generate four check bytes which are appended to the data field. These four
check bytes are the remainder which results when the data field is divided
by the polynomial:
x.sup.31 +x.sup.29 +x.sup.20 +x.sup.10 +x.sup.9 +1.
During a read operation, the data which is being read plus the four ECC
check bytes are also divided by the same polynomial. If no error is
detected, the result should equal zero. If, however, an error is detected,
the rigid disk controller microprocessor 234 enters its error correction
subroutine and begins clocking the ECC generator 252 with a signal
labelled shift/ECC (SHF ECC) until one of two conditions exists: (1) the
signal labelled ECC ERROR is zero or (2) the microprocessor 234 has
executed 5736 shifts and the signal labelled ECC ERROR is high. If the
latter occurs the microprocessor 234 sets an ECC HARD ERROR flag.
The ECC HARD ERROR flag indicates that the microprocessor 234 was unable to
isolate the error or that more than one bit is in error. If the former
condition exists, the signals labelled PAT0 through PAT11 contain the
failing bit pattern and the contents of the microprocessor's B, C, D and E
registers contain the position in memory of the failing data bit.
The ECC generator 252 can detect an error in a 22-bit burst and can correct
a single bit error in an 11-bit field.
A buffer address counter 254, which consists of six devices, such as Model
No. 74LS193 manufactured by TI, is connected to the buffer control 246 by
an ADVANCE BUFFER ADDRESS line and an ADVANCE DMA ADDRESS CONTROL line.
The buffer address counter 254, in turn, is connected to an address
multiplexer 256, which consists of three devices such as Model No. 74LS157
manufactured by TI, to which address multiplexer 256 is fed signals from
the buffer address counter 254 as well as from a microprocessor buffer
address register 258.
The address multiplexer 256 is connected to a 1K.times.8 byte RAM buffer
260, such as Model No. 2148 manufactured by Intel. The RAM buffer 260
receives signals from the address multiplexer 256 as well as from a RAM
data input multiplexer 262, which consists of three devices such as Model
No. 74LS374 manufactured by AMD. Circuitry for processing microprocessor
data is provided at reference numeral 264, which consists of Model Nos.
8304B and 74LS08 manufactured by AMD and is connected via a sequencer data
0-7 bus to the RAM buffer 260 and to the microprocessor data bus 240. A
serializer data register 266, such as Model No. 74LS374 manufactured by
AMD, is connected to the microprocessor data circuit 264, the output of
which data serializer 266 is applied to the serializer/deserializer 248. A
DMA data out register 268 is connected to the RAM buffer 260, to the
microprocessor data circuit 264, and to the serializer data register 266.
A fixed disk drive bus is provided at reference numeral 270. The fixed disk
drive bus 270 transfers data to and from drivers and receivers 272, which
consist of devices such as Model Nos. 7438 and 74LS14 manufactured by TI.
A multiplexer is provided at reference numeral 274, such as Model No. 74S51
manufactured by TI. The multiplexer 274 receives information from the ECC
generator 252. The multiplexer 274 generates a non-return-to-zero write
data (NRZ WR DATA) signal via an NRZ flip flop, such as Model No. 74LS74
manufactured by TI, to a modified frequency modulated (MFM) generator 275
manufactured by TI, and a Model No. DL1708 delay line manufactured by
Valor Elect., Inc. The output of the MFM generator 275 is a series of
clock and data pulses referred to as an MFM WRITE DATA signal for writing
data on one of four fixed disk drives connected to the fixed disk drive
bus 270.
A modified frequency modulated read (MFM READ) signal is applied to a data
separator 276, such as Model No. WD1000 Winchester Disk Controller
manufactured by the Western Digital Corporation of Irvine, Calif.
Error Detection and Correction
Frequently communication systems employ two-way channels, a fact that must
be considered in designing communications systems and signals for use
therewith. With a two-way channel, for example, an error detecting code
can be used. When an error is detected at one terminal, a request for a
repeat transmission can be given, and thus errors can effectively be
corrected.
There are true examples of one-way channels, in which error probabilities
can be reduced with error correcting codes but not by error detection and
retransmission. With a magnetic disk storage system, for example, if
errors are detected when the record is read, it is too late to ask for a
retransmission after the disk has been stored for a week or for a month.
Encoding for error correcting codes is no more complex than is encoding for
error detection; it is the decoding that is likely to require complex
equipment.
There are several reasons for using error detection and retransmission when
possible. Error detection is by its nature a much simpler task than error
correction and requires much simpler decoding equipment. Also, error
detection with retransmission is adaptive. Transmission of redundant
information is increased when errors occur. This makes it possible under
certain circumstances to achieve better performance with a system of this
kind than is theoretically possible on a one-way channel.
There is a limit, however, to the efficiency of a system that uses simple
error detection alone. Short error detecting codes cannot detect errors
efficiently, while if extremely long codes are used, retransmission must
be performed too frequently. A combination of correction of the most
frequent error patterns coupled with detection and retransmission for less
frequent error patterns is not subject to this limitation and, in fact, is
often more efficient than either error correction or detection and
retransmission alone.
In addition to storing bits of data on a medium such as a disk, extra bits
must be stored for a system to detect and/or correct errors. In the ASCII
standard, each alphanumeric character is represented by seven bits. An
eighth bit may be added to each character in storage, as a parity bit or
check bit, to aid in determining whether the preceding seven bits are
correct. The value of the parity bit is zero if the preceding seven bits
add up to an odd number and one if they add up to an even number.
The checksum, which is an accumulation of the remainder of modulo 256
addition of a string of data organized in bytes, is a method of error
detection easily generated and usually effective in detecting errors.
Often, in the case of data which is coded into ASCII characters that
represent the data in hexadecimal form, the checksum is taken over the
values of the hex numbers rather than over the actual bit patterns
themselves. Typically, the initial value of the eight-bit checksum is
minus one. This is so that when zero occurs often in the data, the
effectiveness of the code is not diminished.
The use of parity bits can aid in locating an error only to within the
preceding seven bits. A more complex (Hamming) code employs a greater
number of check bits and yields the precise address of a single bit that
is in error. The correction of the error then requires simply the
conversion of a one into a zero, or the reverse.
In a cyclic redundancy code (CRC) scheme, data bits are treated as the
coefficients of a polynomial which is manipulated algebraically to yield a
smaller set of bits. These bits are stored and retrieved to reconstruct
data in the event of an error or a burst of errors, which is more likely
to occur on magnetic disks.
Much coding theory has been based on the assumption that each symbol is
affected independently by noise, so that the probability of a given error
pattern depends only on the number of errors. Codes have been developed,
for example, that correct any pattern of t or fewer errors in a block of n
symbols. While this may be an appropriate model for some channels, on
magnetic disk storage systems errors occur predominantly in bursts.
Magnetic disk defects are typically larger than the space required to
store one symbol. Consequently, codes for correcting bursts of errors are
required.
Codes are usually described in mathematics as closed sets of values that
comprise all the allowed number sequences in the code. In data
communication, transmitted numbers are essentially random data patterns
which are not related to any predetermined code set. The sequence of data,
then, is forced into compliance with the code set by adding to it at the
transmitter. Thus, a string of original data becomes the original string
concatenated with a string of extra numbers that make the total string one
of allowed code set values.
At the receiver, incoming data is checked to determine whether it is one of
the allowed code set values. The assumption is made that if an error
occurred in transmission, likelihood of the result also being a valid set
member is very low. If the received data string is found to be of the
allowed code set, it is assumed that no errors have occurred and that the
data is valid.
A scheme has heretofore been developed by determining what precise extra
string to append to the original data stream to make the concatenation of
transmitted data a valid member of the code set. A consistent way exists
of extracting the original data from the code value at the receiver and to
deliver the actual data to the location where it is ultimately used. For
the code scheme to be effective, the set must contain allowed values
sufficiently different from one another that expected errors are not able
to alter one allowed value such that it becomes a different allowed value
of the code set.
The CRC code set consists of strings of binary data evenly divisible by a
generator polynomial, which is a selected number that results in a code
set of values different enough from one another to achieve a low
probability of an undetected error. To determine what to append to the
string of original data, a division is made of the original string as it
is being transmitted. When the last data is past, the remainder from the
division is the required string that is added since the string including
the remainder is evenly divisible by the generator polynomial. Because the
generator polynomial is of a known length, the remainder added to the
original string is also of a fixed length.
At the receiver, the incoming string is divided by the generator
polynomial, and if the incoming string does not divide evenly, that is, if
the remainder after division is not zero, then an error is assumed to have
occurred. If the remainder is zero, the data is assumed to be error free,
and the data delivered to the ultimate destination is the incoming data
with the fixed length remainder field removed.
The longitudinal redundancy code (LRC) is a special case of CRC where the
particular generator polynomial chosen results in the same CRC code as
would be obtained by performing a 16-bit wide exclusive OR operation once
every 16 bits. If the data stream were represented as a succession of
16-bit words, the LRC code added to the end of the stream would equal the
first word exclusive ORed with the second, exclusive ORed with the third,
and so on. When the check is made at the receiver, the result is zero if
no errors occurred. This is simply because the exclusive OR of any value
with itself is zero.
As hereinabove implied, the rules under which a system encoder and decoder
operate are specified by the particular code that is employed. One
fundamental type of error correcting code is a block code. The encoder for
a block code breaks the continuous sequence of information digits into
k-symbol sections or blocks. It then operates on these blocks
independently according to the particular code to be employed. With each
possible information block is associated an n-tuple of channel symbols,
where n is greater than k. The result, called a code word, is transmitted,
possibly corrupted by noise, and decoded independently of all other code
words. The quantity n is referred to as the code length or block length.
At the receiver a decision is made, on the basis of the information in the
received n-tuple, concerning the code word transmitted. This decision is a
statistical decision. That is, it is of the nature of a best guess on the
basis of available information and is therefore not infallible.
Referring now also to FIG. 4, the data path sequencer is shown. The data
path sequencer transfers data via DMA operations to or from the memory of
the floppy disk processor 116 into the rigid disk controller 118, to
control DMA requests of the floppy disk processor memory, and to advance
the rigid disk data buffer address.
The data path sequencer consists of 32.times.8 byte random sequencer logic.
The main component is a Model No. 2911 sequencer 410 manufactured by AMD,
which is a 4-bit sequencer with the capability of pushing data on and
popping data off a stack register. The data path sequencer also includes a
Model No. 29811 next address control unit 419 manufactured by AMD, and a
Model No. 74LS151 status multiplexer 418 manufactured by TI.
Operation of the data path sequencer is initialized by a sequence command
(SEQ CMD) control signal into the sequencer 410. This signal releases the
sequencer 410 to allow it to begin its initialization. The sequencer 410
is initialized by removing the zero (ZERO) signal therefrom. At address 0
of the sequencer 410, a PROM memory 412 and 414 is accessed. The PROM
memory 412 and 414 is a 32.times.8 byte device such as Model No. 82S123
manufactured by Signetics. The contents of the PROM memory 412 and 414 are
made available to the sequencer pipe line register 416 and 426. This
register latches the contents of the PROM memory 412 and 414 for decode
execution by the data path sequencer.
A portion of the output of the sequencer pipe line register 416 is fed into
the status multiplexer 418, selector inputs. Three signal lines, labelled
A, B, and C, are used to select one of eight conditions present at the
input of the status multiplexer 418. The selected item of data is then fed
into the next address control unit 419, where a test is performed on the
condition. This test is to determine whether the selected input is valid.
If it is valid, sequencer 410 may be forced into a jump condition within
the PROM memory 412 and 414. That is, a different address may be forced
onto input ports Y0 through Y3 of the sequencer 410. In the event that the
output of the next address control unit 419 indicates that the condition
selected by the status multiplexer 418 is not valid, then the sequencer
410 accesses the next sequential memory location of the PROM memory 412
and 414, and selects a different condition. In the event of a format
command, the sequencer 410 selects a previous condition.
If a disk read operation is performed, a sequencer read (SEQ READ) line,
which is applied to the PROM memory 412 and 414, is active (i.e., in a low
state). The PROM memory 412 and 414 is addressed from address 0 through
15. A read operation indicates to the sequencer 410 that a disk read is
taking place, and that data is being transferred from the disk drive 120
into the rigid disk controller 118. The data path sequencer, in a read
mode, monitors the deserializer available (DSR AVAIL) line applied to the
status multiplexer 418. This line indicates when a data byte is available
from the disk drive 120 for storage into the sequencer RAM data buffer
260.
RAM Buffer Operation
On finding the DSR AVAIL signal active, the data path sequencer generates
an enable deserializer data (EN DSR DATA) signal via device 428 to gate
onto the sequencer data 0-7 bus the data from the serializer data register
266 and to store it in the sequencer RAM data buffer 260.
Termination of the EN DSR DATA signal advances the disk sequencer address
to the next memory location, ensuring that the next data byte from a disk
drive 120 through the deserializer 248 is not stored over the previous
one. This operation continues until 256 bytes of data have been
accumulated, at which point a decision is made as to whether a second data
block is to be transferred.
If a second data block is to be transferred, the sequencer decides whether
buffer space is still available. This decision is performed by monitoring
gates 420, 422, and 424, the output of which is a buffer available (BUFFER
AVAIL) line. If space is still available in the buffer 260 for the
transfer of data, the sequencer begins to fetch the next sequential data
block from the disk drive 120.
At the same time, the transfer of the previously fetched data block to the
floppy disk processor memory is initiated by a sequencer DMA request (SEQ
DMA REQ) signal generated by device 248. This transfer is performed on a
byte-by-byte basis. The sequencer DMA request is made to the floppy disk
processor 116. Once the floppy disk processor 116 has granted the DMA
request, the DMA CYCLE bar signal becomes active, indicating to the
sequencer that the floppy disk processor 116 has received the previous
data byte.
If this byte of data is not the last byte of data in the sequencer RAM data
buffer 260, the sequencer 410 reinitializes the sequencer DMA request. At
the same time, it monitors the status from the deserializer 248 via the
DSR AVAIL line, indicating when a byte of data has been fetched from the
disk. This operation continues until 256 bytes of data have been
transferred from the sequencer RAM data buffer 260 in the case of a single
data block read operation. In the case of a disk read operation involving
more than one block of data, the aforementioned process continues
indefinitely or until the end of a track has been reached.
There are constraints on the transfer of data. The sequencer does not
initialize the disk for the transfer of the next data block until buffer
space is available. The BUFFER AVAIL signal indicates that less than four
blocks (1024 bytes) of data are resident in the sequencer RAM data buffer
260.
It is possible that four blocks of data can reside in the sequencer RAM
data buffer 260 with no space available. In such a case, if another byte
of data is loaded into the sequencer RAM data buffer 260, the contents
thereof are no longer valid. The data path sequencer 410 enters a floppy
disk processor DMA control mode at this point to create data space. Once a
block of data space exists, the lower portion of the sequencer RAM data
buffer 260 is readdressed, placing the buffer 260 in a psuedo rotating
operating mode. That is, initially blocks 0 through 3 of the buffer 260
are loaded sequentially with the first four blocks of data. The fifth
block of data is loaded in the same memory area of the buffer 260 as the
first block (block 0) was loaded. This operation is continued until either
an entire track of data has been transferred or the operation is otherwise
terminated (e.g., less than an entire track of data is transferred). The
new data overwrites the previous data. Data is not continuously shifted
through memory.
In the event that a read error on a block of data is encountered and
detected by the ECC logic of the rigid disk controller 118, the data path
sequencer 410 ceases making disk data requests until it corrects or
attempts to correct the defective data. Some data errors are not
correctable.
Gate 430 and one-shot 432 create a memory write strobe. This strobe is
shorter in pulse width than the enable signals for the data latches. Gate
434, in conjunction with device 428, generates a disk advance (DSK
ADVANCE) signal. This signal advances the disk portion of the address
counter to the memory when an operation involves the transfer of data to
or from the serializer/deserializer 248. Gate 436 generates a DMA ADVANCE
signal to advance the DMA address portion of the memory address counters.
This signal is activated whenever an operation involves the DMA channel
and data is transferred to the floppy disk processor 116. The DMA ADVANCE
line selects the DMA address counter, not the disk address counter. A
write sequencer DMA data (WR SEQ DMA DATA) signal is generated by device
428 via inverter 440 to store the data to be written into the floppy disk
processor memory on the granting of a DMA cycle.
Referring now also to FIG. 5, there is shown a flow chart of the operations
of the data path sequencer. FIG. 5a is a flow chart of a disk write/DMA
read operation for the data path sequencer. The flow chart is contained in
the code which is stored in PROMs 412 and 414 (FIG. 4).
In operation, the disk controller microprocessor 410 initializes a
sequencer read operation. A sequencer read instruction addresses the PROMs
412 and 414 from address 0 to 15. The program flow begins with a start
operation, step 510. The first instruction encountered is a no op
instruction, step 512. At address 2, the sequencer checks its input status
condition to determine whether the operation is a drive command, step 514.
If it is not a drive command, the sequencer generates a DMA request, step
516, advancing the address to 5.
Another condition is checked, step 518, to determine whether operation is
DMA data ready. If so, the sequencer indicates that a byte of data has
been presented by the floppy disk processor 116 to the rigid disk
controller 118. Data is available for the sequencer. If no DMA data ready
occurs, the sequencer stays in its tightly controlled loop, waiting for
the floppy disk processor 116, to present a byte on the bus. If 500
milliseconds have elapsed, step 519, however, progra | | |
