An MOS/LSI type dynamic RAM with single 5 V supply and grounded substrate employs a guard ring surrounding the cell array to prevent pattern sensitivity in testing. The guard ring is an N+ region biased at Vdd over a deep P+ region in a P-substrate, producing a built-in electric field which attracts diffusing minority carriers into a collecting junction. A standard process for making double-level poly memory devices is modified by adding a P+ implant and deep drive-in prior to field oxidation.
An electrically programmable memory cell of a type having a source, a drain, a floating gate and a control gate formed over a face of a semiconductor substrate in which a ring region of material doped similarly to the substrate encloses the source, drain and gates and extends to a surface of the substrate around its length. Drain and source coupling regions of material doped oppositely to the substrate contact the drain and source, respectively, within the ring and extend under the ring to the substrate surface outside of the ring defining drain and source contact regions, respectively. A contact outside the ring to the control gate is provided by a gate coupling region also extending under the ring to a substrate surface on either side thereof. An interconnect couples the floating gate to the gate coupling region. A non-light transmitting, electrically conducting shield extends over the cell contacting the ring region around its periphery at the substrate surface.
On a p.sup.++ substrate (1) provided is a p.sup.- epitaxial layer (2) having an impurity concentration lower than that of the p.sup.++ substrate (1). A p well (3) is formed in a portion of the p.sup.- epitaxial layer 2 and further n.sup.+ diffusion layers (4a and 4b) are selectively formed in the p well (3). A memory cell capacitor (5) is connected onto the n.sup.+ diffusion layer 4b. On the other hand, an no diffusion layer (6) is selectively formed in the p.sup.- epitaxial layer (2) separately from the p well (3), to which an external signal input circuit (7) is connected. Further, a p.sup.++ diffusion layer 9a is provided between the external signal input circuit (7) serving as a source for injection of the minority carriers, i.e., electrons and the n.sup.+ diffusion layer (4b) connected to the memory cell capacitor (5), for blocking the entry of the minority carries. The p.sup.++ diffusion layer (9a) extends up to such a depth as to reach the p.sup.++ substrate (1) from a surface of the p.sup.- epitaxial layer (2). Having this structure, a semiconductor device which does not allow the electrons injected to the p.sup.- epitaxial layer from the external signal input circuit to reach the memory cell capacitor can be provided.
A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks or microcomputers with rapid communication between concurrent processes on the same or different microcomputers.
A semiconductor device comprises a logic circuit and a memory including a timing signal generator circuit, both formed in a substrate, and a wiring connecting the logic circuit to the memory, in which a diffusion layers connected to receive a predetermined potential is located under an area of the wiring situated between the logic circuit and the memory whereby it is possible to alleviate an effect from minority carriers and a substrate potential variation.
A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.
