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System for processing machine check interruption
   
Document Number
US Patent 4587654
Issued Date
May 6, 1986
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Abstract
A system for processing machine check interruption using a data processor which outputs a machine check interruption signal by detecting the generation of a machine check condition and which performs interruption processing on the basis of the machine check interruption signal. The data processor includes a specific code detector which detects a specific interruption signal among the machine check interruption signals, a signal converting circuit for converting the machine check interruption signal into a modified code signal when the interruption signal generated by the machine check interruption is the above-mentioned specific code, and a control portion which assumes a disabled-waiting condition in response to the modified code signal. The operation of the data processor is stopped by placing the control portion in a disabled-waiting condition when interruption of the above-mentioned specific code occurs.
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System for processing machine check interruption - US Patent 4587654 Drawing
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Number of Claims:
4
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Owner
Fujitsu Limited (Kawasaki,JP)
Published
May 6, 1986
Application Number
06/554,730
Filed
November 23, 1983
US Classification
714/34  
Int'l Classification
G06F   11/07   (20060101)  
Attorney/Law Firm
Priority Data
Dec 23, 1982 [JP] 57-228855
USPTO Field of Search
371/14   371/16   371/12   364/200  
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This apparatus stops the clock for a processor partition consisting of a group of processor units in response to detection and classification of an error in a processor unit which can cause a cascade of errors in the partition group.

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Description
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