An object based operating system for a multitasking computer system provides objects which represent the architecture or interrelationships of the system's resources. Access to certain objects is required in order to use corresponding resources in the system. All objects have a consistent data structure, and a consistent method of defining the operations which apply to each type of object. As a result, it is relatively easy to add new types of system objects to the operating system. The object based operating system supports multiple levels of visibility, allowing objects to be operated on only by processes with the object's range of visibility. This allows objects to be made private to a process, shared by all processes within a job, or visible to all processes within the system. An object or an entire set of objects can be moved to a higher visibility level when objects need to be shared. In addition, access to each object is controlled through an access control list which specifies the processes authorized to access the object, and the types of access that are allowed. An object with a restricted access control list can be associated with a "privileged operation", thereby restricting use of the privileged operation to those user processes authorized to access the corresponding object. Waitable objects are used to synchronize the operation of one or more processes with one another or with specified events. The system provides routines for generating new types of waitable objects without modifying the operating system's kernel.

A pipeline computer architecture having two interconnected microengines operating simultaneously in an instruction preparation unit of a pipeline computer system. Each microengine operates on the same portion or different portions of an instruction concurrently within the same clock cycle. To assure coordination, one microengine is declared the executive or attribute generator and the other the main microengine. The main microengine generates routines to control the instruction preparation unit hardware. The executive microengine prepares the next tank in parallel and supplies arguments to the main microengine as the main microengine generates its current routine. At the completion of a routine performed by the main microengine, it signals the executive microengine to obtain the next task and associated parameters.

Bypassing of data from a main storage unit to an instruction and operand processing unit around an intermediate storage unit improves performance in a data processing system. The instruction and operand processing unit supplies requests for operands to the intermediate storage unit or cache. If the line is missing from the cache, the request operand is retrieved from the main storage unit. A bypass data path is connected between the main storage unit, prior to error detecting means in the cache, and the instruction and operand processing unit for transferring requested operands to the instruction and operand processing unit directly. Control, coupled to receive requests for operands and to the instruction and operand processing unit, signals the instruction and operand processing unit to receive the requested operands from the bypass data path when the data includes a requested operand.

A cache coherency scheme in a multiprocessor computer system allows data sharing between caches at a fast rate. A new cache coherency state is introduced which allows a processor pair to more effectively share data and eliminate bus transfers thereby improving system throughput. The transfer of data is accomplished by the returning a portion of a preselected data block pursuant to either a read or a read for ownership request by a first one of the processors of the processor pair by the second processor of the processor pair. The ownership of the portion of the preselected data block is shared by the processor pair. Both processors set an indicator to denote that the preselected data block is an incomplete data block.

A flexible dynamic memory controller that is operable with dynamic RAMS having a wide range of operating characteristics. These characteristics include different operating speeds for various memory functions, and the usage of memories. In a state machine, a special register is utilized to control where in the sequence of operation, and for how long various delays must be inserted. The delays are dynamically determined by the memory controller in accordance with the type of memory being accessed at a given time and the source of the request.