The disclosure describes a separate trace table for each CPU in an MP to avoid inter-CPU interference in making trace table entries for explicit and implicit tracing instructions enabled by flag bits in a control register (CR). Explicit tracing entries are made for an enabled explicit tracing instruction. Implicit tracing entries are made for predetermined instructions (when enabled for tracing) which do not have tracing as their primary purpose. A storage operand of the trace instruction contains a disablement field and optionally may contain an enablement-controlling class field to improve the integrity of traceable programs. A time stamp and range of general register contents is provided in each trace table entry for a tracing instruction. The time stamp enables all trace tables in an MP system to be later merged into a single trace table whenever required.
A task tracing apparatus stores causes and addresses of interruptions, and system call numbers and addresses of system calls issued by an ongoing task. This makes it possible to obtain not only the basic information about switches from one task to another, but also the other related and detailed information as needed. Thus the development of software systems is made easier and more efficient.
Apparatus and method for monitoring transactions on a high speed interface us and for selectively storing information about such transactions together with the time of such transaction and the state of the automaton. The apparatus comprises two parallel memories for respectively storing a regular table and a default table, and a memory selector for choosing between the table data of the two memories. A bus trap stores data information obtained from the bus and compares the stored information with a stored data template. A transition detector receives control signals from the bus and generates clock signals used by other system elements upon the detection of a transition. A hash coder utilizes a hash key together with state information to generate an address for entering the regular table memory. A state latch stores an address provided by the memory selector for the default table. A sample collector and sample queue component stores the state information together with the data and control information obtained from the monitored bus and a time stamp provided by a time stamp generator. A DMA output control provides the sample information to a display computer. The method monitors the interface bus interactions and selectively stores the monitored data and control signals when an analysis of those signals indicate that a transition has occurred. Two parallel, distinct look-up tables store state information and default information and are substantially entered at the same time to provide separate sets of table data. One set of table data is chosen depending upon predetermined criteria.
A simulation input and a model file are generated. The simulation input file is processed to generate object code, entries, line counts, and comment lines. A simulation program is run that uses the object code, entries, line counts, and input comment lines. A machine captures and links output comment lines with their associated test vectors by using the entries and line counts to form a simulation results file. After the simulation, the simulation results file can be reviewed. After simulation, masks (30, 40, 50, 60, 70) are generated that are used to form integrated circuits (20). The present invention can also be used for testing integrated circuits. The test methods use a test input file generated from the simulation results file.
A simulation input and a model file are generated. The simulation input file is processed to generate object code, entries, line counts, and comment lines. A simulation program is run that uses the object code, entries, line counts, and input comment lines. A machine captures and links output comment lines with their associated test vectors by using the entries and line counts to form a simulation results file. After the simulation, the simulation results file can be reviewed. After simulation, masks (30, 40, 50, 60, 70) are generated that are used to form integrated circuits (20). The present invention can also be used for testing integrated circuits. The test methods use a test input file generated from the simulation results file.
A tracer memory (7) stores the history of execution of addresses for the microprogram of an information processing unit to provide clues to the identification of the cause of any exceptional event that may occur in the unit. A pointer register (10) is indexed by one to store in the tracer memory the state of a predetermined group of logical signals at a location designated by the pointer value. When the result of addition to the pointer value surpasses the end address of the tracer memory, the pointer value is changed to the head address of the tracer memory so that data previously written is over written. The tracer memory contains N addresses and on the occurrence of an exceptional event, the current address J in a pointer register is stored in a mask end register 12 and a preceding address I, separated by a predetermined number M of addresses from address J, is stored in a mask start register 11. The value J-M is stored in said mask start register if J-M>0; otherwise, the value {N+(J-M)} is stored. If a second exceptional event occurs during the execution of a failure recovery procedure for the first exceptional event, there is preserved the execution history of the failure recovery procedure caused by the first exceptional event.
