An arbitration apparatus using a least recently used (LRU) algorithm, wherein when a plurality of request devices simultaneously request to use a shared resource, such requests are arbitrated in such a manner that the right to use the shared resource is assigned to the request device with the highest priority. The apparatus includes a priority determining unit for receiving shared-resource request signals from a plurality of request devices and resource using order signals respectively associated with the request devices, thereby outputting a grant signal for the request device with the highest priority along with an arbitration-done signal, a recording register for receiving the grant signal, associated with the use of the shared resource, from the priority determining unit, the recording register storing the resource using order based on the grant signal and outputting the stored data to the priority determining unit, and a status machine for receiving the arbitration-done signal from the priority determining unit along with the request signals from the request devices and other control signals, thereby outputting a status information and control signal to the priority determining unit and a recording register control signal to the recording register.

In a centrally controlled resource arbitration system, each of the units concurrently requesting access sends its identity code and the binary complement thereof to a central arbitration processor. The identity codes are logically combined into a first word, and the binary complements are logically combined into a second word. A subset identifier of the requesting units is then formed by combining corresponding bits of the first and second words. Unresolved values in the subset identifier are iteratively removed to eliminate a subset of the requesting units. When all but one of the requesting units have been eliminated, access to the resource is given to the remaining unit.

A data processing apparatus and method for controlling access to a memory having a plurality of memory locations for storing data values, each memory location having a corresponding address. The apparatus includes address range storage for storing information identifying address ranges for a plurality of logical regions within said memory, and attribute storage for storing, for each logical region, attributes used to control access to memory locations within said logical region. In accordance with preferred embodiments, one or more of these logical regions may overlap with one another. Further, address comparator logic is provided for comparing an address issued by a processor corresponding to one of said memory locations with the address ranges for said plurality of logical regions, and, if one or more of the logical regions contains said address, for generating a signal indicating those logical regions containing said address. Attribute determination logic, responsive to the signal generated by the address comparator logic, is then used to apply predetermined priority criteria to determine which logical region containing said address has the highest priority, whereby the attributes in the attribute storage corresponding to that highest priority region are used for controlling access to the memory location specified by the address.

A rotating priority encoder for selecting from a number of input priority request lines that input request line which is active and which designated as having the highest priority. A mask unit selectively passes only those input request signals which have index numbers which are equal to or greater than a predetermined base-point index number. A 2N priority encoder receives two sets of input signals: L<i>, the masked priority request signals from the mask unit, and H<i> the original priority request signals. The masked priority signals L<i> are given highest priority by this arrangement. The output signal of the 2N priority encoder is the index number of the lowest indexed active input request line. The base-point index number is periodically changed to designate a new input request line as having the highest priority. The masked priority request signals L<i> are assigned the lowest numbers in a sequence of index numbers. The original priority request signals H<i> are assigned the higher numbers in the sequence of index numbers. If the sequence of index numbers for the masked priority request signals L<i> do not end with a number which is an integer power of two, some numbers are skipped before assigning index numbers to the H<i> signals, beginning with a number which is an integer power of 2. For each input request line, the mask unit includes a circuit for determining whether the base-point index number exceeds a the index number of that input request number. The mask units and the 2N priority encoders are easily expanded.

A method and apparatus are described which allow for greater control of interrupt generation to a processor or the like. In one embodiment, a priority selection device is provided which allows a processor or other devices to set the relative priorities among different interrupt requests. The priority information may be dynamic in that it can be modified at other times (e.g., based on the needs of the computer system). A priority resolution device and mask logic device determine which of the generated interrupt requests is of the highest priority and generates an interrupt to the processor to service that high-priority interrupt. In one embodiment, when a processor is servicing an interrupt and a higher priority interrupt is generated, the processor nests the servicing of the higher-priority interrupt in the servicing of the current interrupt. If the newly asserted interrupt request has a priority that is less than the priority of the currently serviced interrupt, the lower-priority interrupt is prevented from being asserted to the processor (until at least the servicing of the higher-priority interrupt is complete, for example).