A digital phase lock loop (PLL) circuit adaptable to a hard disk drive. The PLL operable at a high speed comprises a pulse shaper for subjecting raw data pulses from the disk drive to waveform-shaping, a phase comparator for producing a phase control pulse on the basis of the relative positions of a delayed reference clock (VCLK) pulse and each of said waveform-shaped data pulses from the shaper, and a phase shifter for generating the VCLK pulse in response to the phase control pulse.
A video signal and a horizontal synchronizing signal provided from a work station are delayed by a plurality of delay circuits having different delay amounts, and phase differences between a sampling clock signal and the delayed signals are detected. A clock generator generates two kinds of clock pulses having opposite phases and the same frequency. A clock selector selects one of the clock pulses as a sampling pulse signal in response to the phase differences. Further, a phase difference between the horizontal synchronizing signal and the video signal is detected so that the phase difference between the horizontal synchronizing signal and the video signal is maintained constant.
A harmonic detector including a pattern detector circuit responsive to a clock signal and a data signal configured to detect a target bit pattern from said data signal, and a time-out circuit responsive to said pattern detector circuit configured to detect the absence of said target bit pattern during a predetermined time-out parameter for indicating when said clock signal exceeds said data signal by a factor of two or more.
Apparatus and method are disclosed for implementing a clock and data recovery circuit for use on digital networks. A fully integrated phase-locked loop extracts a clock signal embedded in a data stream. Two trimming digital-to-analog converters simultaneously bring the center frequency of a current controlled oscillator and the phase-locked loop closed loop bandwidth to desired values. A triple sampler captures jittering data and aligns them with the recovered clock. The input jitter tolerance for the method and apparatus is two to three times that of previously reported phase-locked loop based circuits.
Correction for harmonic disturbances on rotating storage media in a phase-locked loop. The effects of harmonic disturbances in a phase-locked loop are reduced by employing harmonic correction. Harmonic correction may be present in the loop at all times, or may be switched in once the loop has achieved phase lock. Disturbance within the loop bandwidth is corrected using additional integrating pole or a bump (resonant) filter. Disturbance outside the loop bandwidth is corrected using low pass or a notch (anti-resonant) filter. Alternately, a canceling signal may be generated and added as a feedforward signal. A repetitive control scheme uses a filtered version of the residual errors on previous media rotations as a feedforward signal to cancel harmonic effects.
According to the method, the clock signal is obtained from a phase increment datum .DELTA.P, representing the frequency to be synthesized. It consists in performing a binary number M modulo addition of each phase increment with the modulo M sum of the phase increments already totalized inside a phase accumulating device. After each overflow of capacity of the accumulator device, the remaining residual phase error P.sub.K is read in the accumulating device. Correlatively, 2.sup.Q clock signals with a period T.sub.c, phase-shifted with respect to each other by T.sub.c /2.sup.Q are generated. A temporal error .DELTA.t.sub.K is computed by obtaining the ratio P.sub.K /.DELTA.P between the residual phase error P.sub.K and the phase increment .DELTA.P per period T.sub.c. Finally that clock signal for which the phase shift with respect to the computation clock signal is closest to the computed residual phase is selected. /
