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BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention in general relates to electrosurgery and in particular to an
electrosurgical unit utilizing solid state electronics.
2. Description of the Prior Art
Electrosurgical generators which produce high frequency electric currents
used for cutting of tissue and coagulation of small blood vessels have
been well-known for at least fifty years. The use of solid state devices
in the electronics, and in particular the amplifiers of such
electrosurgical devices has also been well-known for many years.
The use of so-called cascode configuration in which one electrical
component provides a current gain while another component provides a
voltage gain has been known in the electronics field for at least a
generation. In particular, a cascode configuration consisting of a bipolar
transistor and a field effect transistor (FET) connected in series, called
a hybrid cascode configuration, has been known for many years. See, for
example, United Kingdom Patent Application GB No. 2 053 606 A published
Feb. 4, 1981, and the cascode configuration shown on page 6 of the Modern
Electronic Circuits Reference Manual by John Markus, (McGraw Hill 1980).
Although the cascode configuration of solid state amplification units has
been known for some time, it has not been used in electrosurgical
generator amplifiers. The most common amplifier configuration for
elecrtrosurgical units is the common emitter topolgy employing multiple
parallel bipolar transistors. The only known use of FETS in the
electrosurgical amplifier art has been employed in a full-H-bridge-type
circuit. See United Kingdom Patent Application GB No. 2 105 200 A on an
invention of William Joseph Bowers. In particular, a series-type
configuration in which both of the semiconductors are used as amplifiers,
rather than only as switches, has been believed to be not appropriate for
electrosurgical units. This is because electrosurgical generators require
fast switching at very high power, and significantly, they require the
fast switching to be provided over a wide range of power levels. Such a
use of the semiconductor device necessarily requires that the device be
used in instances when it is not in saturation, in which cases the devices
are highly inefficient. Those skilled in the art have believed that this
would lead to high power dissipation in an electrosurgical unit with the
resultant inefficiency, unreliability, and/or the necessity for
ventilating fans which exhaust non-sterile air into the operating room
environment.
It has for some time been known in the art that an electrosurgical
generator that is capable of producing four different types of waveforms,
including a cutting waveform, a coagulation waveform, a blend of cut and
coagulation, and a fulguration waveform would be highly desirable, since
surgeons commonly may require the use of all four types of functions in a
given surgical procedure. In order to produce such combination type
electrosurgical devices it has been necessary in the prior art to use
highly complex amplification circuitry involved either separate
amplification circuits for each waveform, complex switching arrangements
between the circuit devices which in effect create different circuits for
the various waveforms, or compromises in the performance and efficiency in
one or more of the modes. See, for example, United Kingdom Patent
Application GB No. 2 105 200 A referenced above, U.S. Pat. No. 4,188,927
issued to Frank W. Harris, and U.S. Pat. No. 3,952,748 issued to Paul L.
Kaliher et al.
SUMMARY OF THE INVENTION
I have discovered that it is possible to utilize a hybrid cascode
semiconductor arrangement employing a bipolar transistor and a field
effect transistor in series with the load, and at the same time avoid the
problem of excessive heating leading to unreliability or requiring
ventilation fans. Moreover, I have discovered that by controlling the
voltages applied to the control terminals, (i.e., the base voltage of the
bipolar device and the gate voltage of the FET device) in a particular
manner, this simple amplifier can be adapted to yield all four of the
above-indicated waveforms that are desirable in an electrosurgical unit.
It is an object of the present invention to provide an electrosurgical unit
with a wide variety of functions and simplified circuitry.
It is a further object of the invention to provide a solid state
electrosurgical unit which employs a hybrid cascode amplifier design.
It is another object of the invention to provide an electrosurgical unit
that can be used in an operating room without fans which circulate air.
It is a further object of the invention to provide an electrosurgical unit
which employs an amplifier design having two control devices in series,
each of which has an input port, one of which controls a switch and the
other of which controls the current gain and/or the degree of saturation.
It is another object of the invention to provide an electrosurgical unit
having a hybrid cascode amplification circuit in which the bipolar device
base terminal bias voltage is variable to control the output power of the
unit.
The invention provides an electrosurgical unit comprising a direct current
power source, a means for amplifying connected to the power source
comprising: first and second semiconductor devices each having an input
and an output, and a control terminal for controlling the electrical flow
through the device, the semiconductor devices being connected with their
outputs in series with one another and in series and with the load of said
amplifier; a first voltage control means for applying a control voltage to
the control terminal of the first semiconductor device, the first voltage
control means including a means for varying the control voltage over a
range corresponding to at least a plurality of conducting states of the
first semiconductor device; and a second voltage control means for
applying a control voltage to the control terminal of the second
semiconductor device; and a means for electrically connecting the means
for amplifying to electrosurgical electrodes. Preferably, the first
voltage control means comprises a means for applying a DC or low frequency
signal and the second voltage control means comprises a means for applying
a high frequency signal. The invention in one embodiment includes a means
for applying a varying voltage to the control terminal of the first
semiconductor device for controlling the power of the electrosurgical
unit, and the second voltage control means comprises a means for applying
a signal of fixed duty cycle. The second voltage control means may also
comprise a means for applying a signal of variable duty cycle for
controlling the power of the electrosurgical unit.
Preferably the first semiconductor device is a bipolar transistor and the
second semiconductor device is a field effect transistor. In the preferred
embodiment the invention comprises an electrosurgical unit comprising a
direct current power source, a means for amplifying connected to the power
source, the means comprising: a bipolar transistor connected in series
with a field effect transistor; a first voltage control means for applying
a control voltage to the base of the bipolar transistor; and a second
voltage control means for applying a control voltage to the gate of the
field effect transistor; and also comprises a means for electrically
connecting the means for amplifying to electrosurgical electrodes.
In another aspect of the invention the means for electrically connecting
the amplifier and the electrodes in an electrosurgical unit comprises a
transformer having primary and secondary windings that are wound
concentrically about the same axis and are spaced from each other along
the axis. Preferably a first portion of the secondary winding is wound at
one end of the primary and a second portion of the secondary is wound at
the opposite end of the primary.
The invention provides an electrosurgical unit capable of providing the
cut, coagulation, blend and fulguration radio frequency modes with a
single, simple amplification circuit. Numerous other aspects, features,
objects and advantages of the invention will now become apparent from the
following detailed description when read in conjunction with the
accompanying drawings, in which:
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A through 1C are a block diagrammatic illustration of a preferred
embodiment of the invention; the full electrosurgical unit may be seen by
placing FIG. 1A on the left, FIG. 1B in the center and FIG. 1C on the
right, in which positions the interconnections between the Figs. are
evident;
FIG. 2 shows an electrical circuit diagram of the basic hybrid cascode
amplifier according to the invention;
FIG. 3 is detailed electrical schematic of the hybrid cascode power
amplifier of the preferred embodiment of the invention shown in FIG. 1C;
FIG. 4 is a detailed electrical schematic of the output stage of the
embodiment of the invention shown in FIG. 1C;
FIG. 5 shows the core of the bipolar transformer utilized in the embodiment
of FIG. 4;
FIG. 6 illustrates the method of winding the primary winding on the core of
FIG. 5;
FIG. 7 shows the method of winding of the secondary winding on the core of
FIG. 5;
FIG. 8 is a partial sectional view of the monopolar transformer utilied in
the embodiment of FIG. 4;
FIG. 9 is an external view of the transformer of FIG. 8;
FIG. 10 is a partial sectional end view of the transformer of FIG. 9;
FIG. 11 is a detailed electrical schematic of a portion of the Power Supply
of the embodiment of the invention in FIG. 1A;
FIG. 12 is the power-on reset circuitry of the embodiment of the invention
shown in FIG. 1A;
FIG. 13 is a detailed electrical schematic of the lamp/relay register of
the embodiment of the circuitry shown in FIG. 1A;
FIG. 14 is a detailed electrical schematic of the Gate Waveform
Generator/Driver of the embodiment of the invention shown in FIG. 1B;
FIG. 15 and FIG. 16 show a detailed electrical schematic of the Base
Voltage Generator/Driver of the embodiment of the invention shown in FIG.
1B.
FIG. 17 is a detailed electrical schematic showing the connections to the
microprocessor in the embodiment of the invention shown in FIG. 1A;
FIG. 18 is a block diagram of the microprocessor; and
FIG. 19 is a diagram showing the waveform generator counter states at
specified times of the counter cycle.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIGS. 1A through 1C, an electrosurgical unit according to the
preferred embodiment of the invention is shown. The blocks shown are
divided along functional boundaries. The schematic diagrams in the
following Figs. are divided along the same functional lines where
possible. Connections across physical boundaries are shown where they
apply. Foot switches 10, hand switches (not shown) connected through
outputs 22, front panel switches 10c and 10d and potentiometers 14 (FIG.
1A) control controller circuitry 20 to provide the desired electrical mode
settings within the unit and thus control the electrical power signals at
outputs 22 (FIG. 1C). The Cut and Coagulation mode settings are activated
via the handswitches and the footswitches 10 which are conventional in
electrosurgical units and will not be described further herein. A power
amplifier 23 comprising a first semiconductor device 24 and a second
semiconductor device 25 provides the electrical power to the outputs 22
through output circuitry 30. A first voltage control means 34 comprising
Base Voltage Generator/Driver (FIG. 1B) applies a control voltage to
control terminal 27 of first semiconductor device 24, and a second voltage
control means 33 comprising Gate Waveform Generator/Driver 33 applies a
control voltage to control terminal 28 of second semiconductor device 25.
Outputs 22 are conventional electrosurgical connectors for the particular
electrodes indicated, and comprise a means for electrically connecting the
output circuitry 30 and the means for amplifying 23 to electrosurgical
electrodes.
The power for the electrosurgical unit is provided by Power Supply (source)
36 (FIG. 1A). The Power Supply 36 converts the AC mains power to the
various DC supply voltages required by the circuitry.
In one aspect of the invention, switches 10 and 10c, potentiometers 14 and
multiplexer 54 comprise a means for producing a predetermined first
digital signal representative of a desired characteristic of the unit. In
this aspect of the invention a portion of power supply 36 (shown in FIG.
11) comprises a means for producing a second digital signal representative
of an operating characteristic of the electrosurgical unit.
The Controller 20 embodies the intelligence of the unit. It responds to
user commands, communicates with the user via displays and tones, directs
and supervises the activities of all other modules in the system, performs
fault detection and aids in diagnosis. The Controller 20 includes a memory
50a (FIG. 18) which is a means for storing the signal representative of a
desired characteristic of the unit.
The Display 37 provides the user with visual indications of current power
settings for each mode, Pure/Blend mode selection, Bipolar Hi/Lo mode
selection, which mode is currently activated and indication of fault
conditions requiring the user's attention.
The Gate Waveform Generator/Driver 33 (WFG) produces the FET gate 28 drive
signals for the power amplifier under control of the microprocessor 50. It
includes circuitry 80 for producing a signal (COAG-Q) which is utilized to
suppress the voltage limitation effect (see below) when the system is in
Coagulation mode.
The Base Voltage Generator/Driver (BVG) 34 supplies base current to the
power amplifier bipolar transistors 24 at a voltage appropriate to the
mode of operation. It includes circuitry 92, 95, 111 for limiting the
voltage at the outputs 22.
In one aspect of the invention, the WFG 33 and the portions of the
Controller 20 other than memory 51a comprise a means responsive to a first
digital signal and a second digital signal for controlling an output means
of the electrosurgical unit. In another aspect of the invention the BVG 34
and the portions of the Controller 20 other than the memory 50a comprise
such a means for controlling an output means.
The Power Amp (PA) 25 responds to its input signals in a fashion necessary
to produce therapeutically useful RF currents.
The RF Output circuitry 30 transfers the RF power generated by the power
amplifier 23 to the output connector panel.
In one aspect of the invention the display 37 comprises an information
output means of the unit. In another aspect of the invention the Power Amp
25 and the output circuitry 30 comprise a therapeutic output means of the
electrosurgical unit.
The Continuity Detector 39 delivers to the microprocessor 50 the status of
various contacts (not shown) in the isolated RF output circuit. The
contacts are those of the conventional hand-switchable bipolar and active
monopolar accessories and the two wire patient plate circuit, which are
connected to outputs 22.
We turn now to a more detailed description of the electrosurgical unit,
while referring to FIGS. 1A through 1C. The names such as /PROG and ALE on
the lines connecting blocks indicate the designation of the signal which
shall be useful in the discussion of the operation of the unit below. The
/ in front of a signal such as in /PROG indicates the inverted signal.
Power Supply 36 is connected to an AC outlet by power plug 40. The unit is
turned on or off via switch 41 between power plug 40 and isolation power
transformer 42. Power Supply 36 converts the AC outlet power to the
various DC supply voltages required by the unit. The nominal supply values
are shown at the right of power supply 36 in FIG. 1A, and include two
switched power supplies 43 and 44 which enhance the safety of the unit.
Controller 20 includes microprocessor 50, the timing for which is provided
by a crystal oscillator 51. A signal from the 12 volt unregulated output
of power supply 36 is applied to the microprocessor 50 at input AN1.
Controller 20 further includes multiplexer 54 which multiplexes and feeds
the signals from controls 10 and 14 to microprocessor 50. Controller 20
also includes multiplexer register 57, audio generator 58,
expander-decoder 60, lamp/relay register 61 and associated buffers 62 and
63, power on reset circuitry 64 and watchdog timer 65. A signal, ISENSE,
is supplied to multiplexer 54 from power supply 36 which is representative
of the current drawn from the 120 volt power supply output. This is
calibrated by current sense resistor 45. Control signals for the
multiplexer 54 are provided from the microprocessor 50 and
expander-decoder 60 outputs via multiplexer register 57. Audio generator
58 is controlled via outputs from microprocessor 50 and expander-decoder
60 to produce a signal to drive speaker 59. The volume of the audio
generator 58 is controlled via volume control 66 and a loud/soft signal
generated by microprocessor 50. Expander-decoder 60 receives output
signals from microprocessor 50 which are demultiplexed by expander-decoder
60 using synchronization signals /PROG and ALE which are also provided to
expander-decoder 60 by microprocessor 50. The output signals of
expander-decoder 60 are provided to multiplexer register 57, audio
generator 58, the decoder/driver 70 of the display circuitry 37 (FIG. 1B)
the Gate Waveform Generator register 80, the watchdog timer 65 and the
lamp/relay register 61. The lamp/relay register 61 receives output signals
from microprocessor 50, expander-decoder 60, and power-on reset circuitry
64 and in turn applies output signals to display circuitry 37 (FIG. 1B)
and output circuitry 30 (FIG. 1C) via buffers 62 and 63 respectively. The
power-on reset circuitry applies signals to the lamp relay register 61,
the microprocessor 50, and the watchdog timer 65. The watchdog timer 65
uses its own internal timing signals and the inputs from expander-decoder
60 and power-on reset 64 to provide control signals to power relay
switches 43 and 44 and microprocessor 50. The microprocessor 50 also
receives input signals from continuity detector 39 (FIG. 1C) and applies
control signals to gate driver 88 and base voltage multiplexer 95 (FIG.
1B).
Turning now to the circuit of FIG. 1B, the Display circuitry 37 includes
decoder/driver 70, seven segment LED display 71, mode indicators 72, 73
and 74, alarm indicators 75, 76, and 77, inverter 78, and resistor 79. The
signals from the microprocessor 50 and expander-decoder 60 are decoded by
the decoder/driver 70 which in turn drives display 71. Signals from the
lamp/relay register 61 drive mode indicator 72, 73, and 74 and alarm
indicator 75 and 76. A signal from the detector 109 is also applied to the
plate alarm indicator 76 via inverter 78 and resistor 79. A signal from
the watchdog timer 65 drives machine alarm indicator 77.
The Gate Waveform Generator/Driver circuitry includes waveform generator
register 80, 18 MHz oscillator 81, waveform generator counter 84, offtime
decoder 85, blend counter 86, and gate driver 88. The waveform generator
register 80 receives inputs from microprocessor 50, expander-decoder 60,
and waveform generator counter 84 and applies control signals to waveform
generator counter 84, OFFTIME decoder 85, base voltage multiplexer 95 and
blend counter 86. The waveform generator counter 84 receives a timing
signal from oscillator 81, the preloaded ONTIME signal from waveform
generator register 80, and a signal from OFFTIME decoder 85 and in turn
provides signals to waveform generator register 80, OFFTIME decoder 85,
blend counter 86 and gate driver 88. The blend counter receives the
above-indicated signals and applies a signal to the OFFTIME decoder 85
which in turn applies a signal to waveform generator counter 84 in
response to the signals previously described. The signals from the
waveform generator counter 84 and the microprocessor 50 control the gate
driver 88 to produce the gate drive output signal which is applied to the
gate of the field effect transistors 25 in the Power Amplifier 23.
Base Voltage Generator/Driver 34 comprises feed forward gain compensator
90, cut power calibration potentiometer 91, cut reference voltage
amplifier 92, coag drive voltage divider 93 comprising resistors 93a and
93b, cut drive voltage potentiometer 94, base voltage multiplexer 95,
operational amplifier 97, and base driver amp 98. A voltage signal
produced by potentiometer 91 is applied to feed forward gain compensator
90 which in turn applies a voltage to cut reference amplifier 92. Other
inputs to cut reference amplifier 92 are the +5 reference voltage and a
voltage signal, VCOLL from the output voltage sense circuitry 111 in
output stage 30 (FIG. 1C). Resistor 93a is connected between voltage
divider 93 and the +15 power supply while resistor 93b is connected
between the ground and the voltage divider. The output of cut reference
operational amplifier 92 is applied to the base voltage multiplexer 95
through potentiometer 94 which is controlled by cut power control 99. The
other side of potentiometer 94 and the base voltage multiplexer 95 are
connected to ground. The control signals for the base voltage multiplexer
95 are provided by outputs of gate waveform generator register 80 and
microprocessor 50. The output of base voltage multiplexer 95 is applied to
the non-inverting input of operational amplifier 97, while the inverting
input is connected via a voltage divider (FIG. 15) to the output of base
driver 98. The output of operational amplifier 97 is applied to the input
of base driver 98 and the +15 volt RF power supply is also applied to base
driver 98. The output of base driver 98 is applied to the base of the
bipolar transistors 24 in power amp 23.
Turning now to FIG. 1C, Continuity Detector 39 comprises 100 KHz
oscillator/driver 100, toroidal transformer 101, isolated power supplies
102, emitters 103, and detectors 106. The oscillator driver 100 drives the
primary circuit of transformer 101, the secondaries of which in turn drive
isolated power supplies 102. The outputs of the power supplies 102 are
applied to the emitters 103 which are also connected to the switches (not
shown) for the hand, foot, plate, and bipolar electrodes through
connectors 22. The light from the emitters 103 is detected by detectors
106. Detector 109 which is associated with the emitter which is connected
to the plate electrode is applied to the plate alarm indicator 76 as
indicated above, and also to the microprocessor 50. The outputs of
detectors 106 are applied to microprocessor 50.
Output stage 30 comprises output relays 110 (which include switches 115 and
116), output voltage sense circuitry 111, monopolar transformer 112 which
includes a sense winding 113, bipolar transformer 114, and four capacitors
such as 118a. The inputs to the output relays are from the lamp/relay
register 61 (FIG. 1A) and the 24 volt relay output voltage. The physical
connection between the output relays and the switches 115 and 116 is shown
by a dotted line. One side of both monopolar and bipolar transformers 112
and 114 is connected to the +120 volt unregulated power supply while the
other side is connected to Power Amp 23 through switch 115. One side of
sense winding 113 is connected to ground while the other side is applied
to output voltage sense circuitry 111. One side of secondary 208 of
monopolar transformer 112 is connected to the outputs 124, 125, and 126
for the hand and foot controlled monopolar electrodes through switches 116
and capacitor 118a. The other side is connected to ground through the
leakage cancellation circuitry 117 and to the plate electrode output 123
through capacitor 118b. One side of the secondary 209 of bipolar
transformer 114 is connected to one of the terminals of bipolar output 122
through capacitor 119a while the other side is connected to another of the
terminals of bipolar output 122 through capacitor 119b.
The Power Amplifier circuitry 23 has already been discussed above and will
be discussed in considerably more detail below.
FIG. 2 shows a simplified embodiment of the basic hybrid cascode amplifier
of the present invention. The simplified circuitry of FIG. 2 will be
useful in understanding the preferred embodiment of the hybrid cascode
amplifier which is shown in FIG. 3. In the basic amplifier of FIG. 2 the
FET device 25 and the bipolar device 24, a diode 130 and the
electrosurgical unit load 131 (which is the amplifier load) are connected
in series between ground and the +120 volts power supply. More
particularly, the source terminal 25a of the FET 25 is connected to ground
while the drain 25b of the FET 25 is connected to the emitter 24a of the
bipolar transistor 24. The collector 24b of the bipolar transistor 24 is
connected to the cathode of the diode 130 while the anode of the diode is
connected to one side of the load 131. The other side of the load is
connected to the positive voltage supply. The control terminal or gate 28
of FET 25 is connected to a voltage source 134 designated VGATE which in
terms of the preferred embodiment of the present invention is the output
signal of the Gate Waveform Generator/Driver circuitry 33 (FIG. 1B). The
other side of the voltage source 134 is connected to ground. The control
terminal or base 27 of bipolar transistor 24 is connected to a voltage
source designated as VBASE through resistor 137 which is designated Rb. In
terms of the preferred embodiment of the invention, the voltage source 139
is the output signal of the Base Voltage Generator/Driver 34. The other
side of the voltage source 139 is connected to ground. The base 27 of
bipolar device 24 is also connected to ground through capacitor 135
designated as Cb. This is a bypass capacitor which stores the turnoff
charge of bipolar device 24.
Turning now to FIG. 3, the hybrid cascode stage of the preferred embodiment
of the invention is shown. It consists of two separate hybrid cascode
sections connected at the collector bus 144. One section comprises FET 146
and bipolar transistors 147, 148, and 149, while the other section
comprises FET 152 and bipolar transistors 153, 154, and 155. Since the
circuitry associated with each of the FETs is identical, and the circuitry
associated with each of the bipolar transistors is identical, the
circuitry shall be described for only the FET 146 and the transistor 148.
The circuitry associated with FET 146 comprises zener diode 157 and
resistors 158 and 159. The cathode of diode 157 is connected to the line
160 carrying the incoming gate drive voltage, while its anode is connected
to the source, S, of FET 146. Resistor 158 is connected between the
cathode of diode 157 and the gate of FET 146 in the line 160 carrying the
gate voltage to the gate. Resistor 159 is connected between the gate, G,
of FET 146 and the anode of diode 157. The anode of diode 157 and the
source, S, of FET 146 are grounded. The circuitry associated with
transistor 148 includes resistor 162, capacitors 163 and 164, fuses 165
and 168, resistor 166, and diode 167. Resistor 162 is connected between
the drain, D, of FET 146 and the emitter, E, of transistor 148. Fuse 165
is connected along the line 169 carrying the base drive voltage VBASE to
the base, B, of transistor 148. Resistor 166 is also connected along the
base voltage input line 169 between fuse 165 and base, B. Capacitor 163 is
connected between line 169 and ground at a point between fuse 165 and
resistor 166, while capacitor 164 is connected between base, B, and
ground. The cathode of diode 167 is connected to the collector, C, of
transistor 148 while the anode of the diode is connected to one side of
fuse 168. The other side of fuse 168 is connected to the collector bus
144. The drain, D, of FET 146 is connected to the anode of diode 171 and
the cathode of the diode is connected to the 120 volt voltage source
through resistor 172. Zener diode 173 and capacitor 174 are connected in
parallel between the cathode of diode 171 and ground, with the anode of
diode 173 being connected to the ground side. Likewise, the line 169 is
connected to ground through a parallel zener diode 176 and capacitor 177,
with the anode of diode 176 being toward the ground side. The collector
bus 144 is connected to the output circuit (FIG. 4).
Turning to FIG. 4, the collector bus is connected to either the monopolar
transformer 112 or the bipolar transformer 114 depending upon the position
of switch 115. Much of the output circuit 30 of FIG. 4 has been discussed
in reference to FIG. 1c, and thus we shall here discuss only those aspects
of the circuit which were not discussed therein. The output relay
circuitry 110 includes relay coils 181, 182, and 183 which act on the
corresponding relay contacts 116A through 116C and coil 184 which acts on
contact 115. The relay coils 181 through 183 are connected between the
input lines /H1-K, /H2-K, /FT-K respectively, and the +24 relay supply
voltage. Coil 184 is connected between the /BIP-K input line and the +24
relay supply voltage. Diode 186 is connected in series with the coil 184
along the /BIP-K input line with its anode toward the coil. Capacitors,
such as 185, are connected between each of the four input lines and
ground. The input lines are connected to the corresponding signal lines
shown as outputs (TO OUTPUT) in FIG. 13.
The output voltage sense circuitry 111 includes SENSE winding 113, diode
190, capacitors 191, 194, and 195, and resistors 192 and 193. The anode of
diode 190 is connected to one side of the SENSE winding 113, while the
cathode is connected to the anode of diode 415 (FIG. 16) through resistor
192. The other side of SENSE winding 113 is connected to ground. Capacitor
191 is connected between the cathode of diode 190 and the ground line from
the SENSE winding 113. Resistance 193 and capacitors 194 and 195 are
connected in parallel between the VCOLL voltage line and the ground line.
The transformer primary circuitry includes resistors 201 and 202 and
capacitors 203, 204, and 205. Resistor 201 and capacitor 203 are connected
in parallel between the 120 volt supply voltage line and the collector bus
line. Resistor 202 is connected between the 120 volt line voltage line and
the side of primary 207 to which the collector bus is applied. Bipolar
transformer 114 includes primary 206, secondary 209, and core 210.
Monopolar transformer 112 includes primary 207, secondary 208, and core
211.
The leakage cancellation circuitry 117 includes capacitors 212 and 213,
inductance 214, and resistance 215. The four are connected in series, in
the order just given, between the side of the monopolar secondary which
goes to the patient plate and ground.
Turning now to FIGS. 5 through 10, the construction of the transformers
shall be disclosed in detail. The construction of the bipolar transformer
114 is shown in FIGS. 5 through 7. The unwrapped core 210 is shown in FIG.
5. The portion of core 210 which will contact primary 206 and secondary
209, is covered with insulating tape 221. FIG. 6 shows the winding of the
preferred 12 turns of the primary 206 on the core 210. FIG. 7 shows the
winding of the preferred 13 turns of the secondary 209 on the core 210.
Preferably, the primary and secondary are wound concentrically about the
same axis, six turns of the secondary 209 are wound at one end 206a of the
primary 206, another six turns are wound at the other end 206b, and there
is one turn crossing over the primary 206. The primary is covered by a
layer of insulating tape 220 in FIG. 7. After the secondary is wound, it
is also covered by insulating tape.
FIGS. 8, 9, and 10 show the construction of the monopolar transformer. The
transformer is built on a nonconductive bobbin 229 which consists of a
hollow cylinder 230 having four dividers 231, 232, 233, and 234 attached
to its outer surface. The shape of the dividers is rectangular on one end
and circular on the other as shown best in FIG. 10. The primary winding
207 is wound between the center dividers 232 and 233 with the ends of the
primary 207 passing through holes such as 251 (FIG. 9) in the dividers.
The secondary winding 208 is wound between the dividers 231 and 232 and
then passes through holes 253 and 254 in dividers 232 and 233
respectively, crossing the primary winding 207, and is then wound between
dividers 233 and 234. Thus as in the bipolar transformer, the primary 207
and secondary 208 are wound concentrically and a first portion 208a of the
secondary 208 is wound at one end 207a of the primary 207, while a second
portion 208b of the secondary 208 is wound at the other end 207b of the
primary 207. The ends of the secondary are looped through holes, such as
256, in the dividers 231 and 234. Each of the windings are covered with
insulated tape, 235. Preferably the primary winding has 71/2 turns of wire
with the direction of the winding passing from front to rear at the lower
portion of FIG. 8. Preferably the secondary winding has 27 turns with 8
turns in the first layer 258, 7 turns in each of the second and third
layers and 5 turns in the fourth and outer layer. It is preferably wound
in a counter-clockwise direction passing from right to left in FIGS. 8 and
9. The core 211 of the monopolar transformer consists of four cylindrical
ferrite core pieces 240, 241, 242, and 243 which fit inside of cylinder
230 of bobbin 229. The core pieces 240 through 243 have a cylindrical bore
passing through their centers. Rod 246 having threaded ends passes through
the centers of core pieces 240 through 243. Nonconductive washers 244 and
245 fit over the ends of bobbin cylinder 231 and are held in place by nuts
247 and 248 which are screwed on to the ends of rod 246. Hot melt adhesive
233 is melted into one end of cylinder 231 to hold the cores 211 firmly in
position. SENSE winding 113 is preferably a single wind about primary 207,
preferably at the end of the primary 207 connected to the 120 volt line
rather than the end connected to the collector, again wound in the
counter-clockwise direction. The ends of SENSE winding 113 are twisted
together as shown at 259.
Turning now to FIGS. 11 through 15, detailed circuitry pertaining to the
inventive aspects of the electrosurgical unit are shown. FIG. 11 shows the
details of the 12 volt unregulated power supply and the production of a
signal, AN1, which is fed into the microprocessor, and used by the
microprocessor to regulate the duty cycle of the coagulation and bipolar
outputs to produce a uniform output power despite variations of the mains
voltage. The circuitry of FIG. 11 comprises a means for producing a second
signal representative of an operating characteristic of the
electrosurgical unit. This signal is digitized by the A/D converter 50h
(FIG. 18) in the microprocessor as will be discussed below. The power
supply circuitry includes AC plug 40, a lighted circuit breaker 41 which
includes single pole double throw breaker switch 41a and 41b, resistor 268
and light 267 which indicates the on or off condition of the circuit
breaker 41, transformer 42a, bridge rectifier 272, and capacitors 275
through 277. The symbol 273 indicates that the two wires are a twisted
pair. Voltage regulator 280 and capacitor 281 comprise circuitry to
produce the 5-volt regulated power supply. The green wire of plug 40 is
connected to chassis, the white wire is connected to one side of primaries
270a and 270b through circuit breaker 41a, while the black wire is
connected to the other side of the primaries through circuit breaker 41b
and thermofuse 269. The two outputs of the transformer secondary 270c are
applied across bridge rectifier 272. Capacitors 275, 276, 277, and 281 are
connected in parallel across the outputs of bridge rectifier 272. The
negative output of rectifier 272 is grounded and the positive output
provides the 12-volt unregulated power supply. The positive output of
bridge 272 is also applied to the input of voltage regulator 280, while
the common line is attached to the negative side of the rectifier 272
which is grounded. The output of voltage regulator 280 provides the 5-volt
regulated power supply. The circuitry for providing a signal
representative of the unregulated 12-volt power supply, which varies
directly as the mains voltage, as a control signal to the microprocesser
comprises resistors 284, 286, 290, and 291, capacitors 285, and 292, and
potentiometer 287. The 12-volt power supply is applied to one side of
resistor 284 and the other side is grounded through capacitor 285 and also
connected to resistor 286. The other side of resistor 286 is connected to
one input and the output of potentiometer 287. The other input of
potentiometer 287 is grounded through resistor 290. The output of
potentiometer 287 is applied through resistor 291 to the microprocessor
(FIG. 1a) to provide the input signal for power regulation. The output
line 293 is grounded through capacitor 292.
FIG. 12 shows the details of the power-on reset circuitry which insures
orderly power up of the electrosurgical unit. It includes capacitor 297,
resistor 298, diode 299, three input NAND GATE 300, and inverter 304. The
three inverted inputs of NAND GATE 300 are connected to ground through
capacitor 297 and the 5-volt power supply through resistor 298. They are
also connected to the 5-volt power supply through diode 299, with the
cathode of the diode toward the power supply. The output of NAND GATE 300
provides the POR signal to microprocessor 50 and is also applied to the
input of inverter 304. The output of inverter 304 provides the /POR signal
to the lamp/relay register 61 and the watchdog timer 65.
FIG. 13 shows detailed circuitry of the lamp/relay register 61 and the gate
waveform generator register 80, both of which receive the P10 through P17
signals from the microprocessor 50. In FIGS. 13 through 17 the numeric
characters located adjacent to the inputs and outputs of an integrated
circuit chip such as 61a (in the center of FIG. 13) | | |
