A power-on reset circuit for providing a reset signal to an active device on an integrated circuit (IC). The circuit includes a RC circuit for producing a reset signal until its capacitor fully charges. The circuit also includes a voltage detector for preventing the charge from collecting on the capacitor of the RC circuit until the voltage is at a functional level.

A circuit configuration for generating a reset signal includes a bistable switch element assuming a preferential state upon application of a supply voltage. The bistable switch element has an output carrying a reset signal in the preferential state and has an input. An on and off switchable reference voltage source has a control input connected to the output of the bistable switch element. The on and off switchable reference voltage source is switched on in the preferential state of the bistable switch element. An on and off switchable delay line has a control terminal connected to the output of the bistable switch element, an output connected to the input of the bistable switch element, and a reference input connected to the on and off switchable reference voltage source for switching on the delay line in the preferential state of the bistable switch element. The bistable switch element is switched out of the preferential state with a time delay when the supply voltage exceeds a reference value specified by the on and off switchable reference voltage source.

A power-on reset circuit is provided, which includes a ground input, a power input having a voltage relative to the ground input, a reset output, a self-initializing latch, a high voltage trigger circuit and a discharge circuit. The self-initializing latch has first and second latch nodes which are initialized to logic high and low states, respectively, upon initial application of power to the power input. One of the first and second latch nodes is coupled to the reset output. The high voltage trigger circuit is coupled to the first latch node and reverses the states of the first and second latch nodes when the voltage rises above a high trigger voltage. The discharge circuit is coupled to the second latch node and has a switch circuit, which selectively couples the second latch node to the ground input when the voltage falls below a low trigger voltage.

A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

A reset signal generating circuit has a voltage dividing circuit for dividing a power source voltage into a divided voltage, a first switching part controlled responsive to the divided voltage from the voltage dividing circuit and turned ON when the power source voltage rises to a value in a vicinity of a predetermined value with an arbitrary rising speed, a second switching part controlled responsive to an output signal of the first switching part and turned ON during a time in which the first switching part is ON, and a charging and discharging part including a capacitor supplied with an output signal of the second switching part for starting a charging operation from a first time when the second switching part turns ON. The charging anc discharging part outputs a reset signal for a constant time from the first time to a second time and stops to output the reset signal after the second time.