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RELATED APPLICATIONS
The following patent applications, which are assigned to the same assignee
as the instant application, have related subject matter and are
incorporated herein by reference. Certain portions of the system and
processes herein disclosed are not our invention, but are the invention of
the below-named inventors as defined by the claims in the following patent
applications:
U.S. patent application Ser. No. 663,096 entitled, "Distributed Control
Store Word Architecture", having inventors Richard P. Kelly and Thomas F.
Joyce.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The method and apparatus of the present invention generally relates to a
method for recovering from a memory read error in an instruction word used
to control a programmable device and, more particularly, to a method for
recovering from a control store memory read error of a microinstruction in
a microprogrammed electronic data processing system.
2. Background of the Invention
It is common practice today to implement data processing systems in which
the software instruction is executed by use of microprocessors which are
firmware controlled. In this system, the firmware is stored as a series of
microinstructions in a memory referred to as a control store. The control
store may be a random access memory (RAM) which can be written into, as
well as read from, or it may be a read only memory (ROM) of one type or
another. In either case, as the use of firmware increases with more of the
logic of systems being microprogrammable, and as faster memories are used
in order to decrease the time required to perform operations, it is
becoming more likely that a read error will occur when microinstructions
are read from the control store. Many of the errors which occur when
reading data from RAMs and ROMs are of a transient nature and will not
recur if the same data is read a second time from the memory.
One method of detecting a memory read error is to store one or more parity
bits with the instructions and to compute the parity of the instruction
read from memory and compare it with the parity bit or bits stored with
the instruction and if there is a mismatch to go back and read the
instruction again. Although this scheme works, it has the disadvantage
that execution of the program is delayed because an instruction cannot be
executed until its parity is computed and compared with the stored parity.
One method of overcoming this delay associated with checking the parity of
each instruction before it is executed is to prefetch instructions so that
the parity of one instruction can be checked while a previously checked
instruction is being executed. Although this scheme can be used to
advantage to eliminate the delays associated with checking parity prior to
instruction execution, it has the disadvantage that it can become quite
complex and therefore costly because the execution of one instruction will
often determine which is the next instruction to be executed and therefore
prefetching the "next" instruction can be very complicated or impossible.
One method of simplifying this prefetch problem is to prefetch the "normal
next" instruction and check it for possible read errors and if the normal
next instruction turns out not to be the "next" instruction, the "normal
next" instruction is discarded (i.e., flushed from a buffer) and the
system waits while the "next" instruction is read and checked. Even this
"flushing" scheme can be complex and still result in delays each time the
instructions aren't executed in the "normal" sequence.
Therefore, what is needed is a method of detecting and correcting
instruction memory read errors which is simple and which does not
adversely effect the execution time of the system.
OBJECTS OF THE INVENTION
Accordingly, it is an object of the present invention to provide a simple
method of detecting and recovering from instruction read errors in a
programmable device.
It is another object of the present invention to provide a method of
detecting and recovering from instruction read errors that does not
adversely affect the execution time of instructions read without errors.
It is a still further object of the present invention to provide a low cost
method of detecting and recovering from read errors in instructions
controlling a programmable device.
This invention is pointed out with particularity in the appended claims. An
understanding of the above and further objects and advantages of this
invention can be obtained by referring to the following description taken
in conjunction with the drawings.
SUMMARY OF THE INVENTION
The present invention provides for instruction read error detection and
recovery by permitting the unchecked instruction to be executed in
parallel with instruction read error detection by providing for the
aborting of the instruction execution upon detection of an error prior to
making any change in the state of the system which would prevent the
retrying of the instruction after it is read again from memory. Because
the reading of the next instruction is initiated during the execution of
the current instruction whose validity is checked in parallel with its
execution, the present invention provides for the discarding of the next
instruction prior to retrying the current instruction by rereading the
current instruction followed by re-execution of the current instruction.
While the current instruction is being re-executed, the rereading of the
next instruction is initiated so that it will be available for execution
following the re-execution of the current instruction.
BRIEF DESCRIPTION OF THE DRAWINGS
The manner in which the method of the present invention is performed and
the manner in which the apparatus of the present invention is constructed
and its mode of operation can best be understood in light of the following
detailed description together with the accompanying drawings in which like
reference numbers identify like elements in the several figures and in
which:
FIG. 1 is a block diagram of a data processing system incorporating the
present invention;
FIG. 2 is a more detailed logic block diagram of the microprocessor of FIG.
1;
FIG. 3 is a more detailed logic block diagram of the parity
calculator-checker and the clock generator of FIG. 1; and
FIG. 4 is a timing diagram of various clocking, control store addressing,
and control store data signals used by the logic of FIGS. 2 and 3.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention provides for instruction read error detection and
recovery by permitting the unchecked instruction to be executed in
parallel with instruction read error detection by providing for the
aborting of the instruction execution upon detection of an error prior to
making any change in the state of the system which would prevent the
retrying of the instruction after it is read again from memory. Because
the reading of the next instruction is initiated during the execution of
the current instruction whose validity is checked in parallel with its
execution, the present invention provides for the discarding of the next
instruction prior to retrying the current instruction by rereading the
current instruction followed by re-execution of the current instruction.
While the current instruction is being re-executed, the rereading of the
next instruction is initiated so that it will be available for execution
following the re-execution of the current instruction.
The central processor unit (CPU) and other elements comprising the
electronic data processing system of the preferred embodiment of the
present invention are illustrated in FIG. 1. In FIG. 1, the CPU is
comprised of those elements above main bus 127. The CPU communicates with
the other elements in the system through lines 146 which contain address
data and control lines to main bus 127. Main bus 127 is also comprised of
address, data and control lines and serves as the main path for
information which is communicated between main memory 129 and peripherals
131 and 133. Main memory 148 stores data and software program instructions
which are executed by the CPU. Main memory 129 is connected to main bus
127 by lines 148. Peripherals 131 and 133, which are connected to main bus
127 by lines 150 and 152 respectively, are input/output units which are
used to enter, retain or output data into and out of the system.
The logic of the central processor unit can be divided into four groups as
shown in FIG. 1. Microprocessor 101 performs the basic arithmetic and
logic operations of the central processor unit by executing the software
instructions of the software program stored in main memroy 129. Virtual
memory management unit 103 converts the virtual memory addresses contained
in the software instructions into a physical address which is passed to
cache memory 107 on lines 140. In the preferred embodiment, a 30 bit
physical address is calculated by virtual memory management unit 103. This
30 bits of address is indicated by the number 30 next to the diagonal
slash on line 140. Cache memory 107 takes the physical address provided by
virtual memory management unit 103 and does either a read memory or write
memory operation from or to main memory 129 or retrieves the data or
software instruction from its own internal memory. The information
retrieved from cache memory 107 is provided to microprocessor 101 or
virtual memory management unit 103 through processor bus 138 which is a 32
bit wide bus. Glue logic 105 contains miscellaneous logic which ties
microprocessor 101, virtual memory management unit 103 and cache memory
107 together and, as illustrated in FIG. 1, contains a parity
calculator-checker 121 and clock generator 125.
The central processor unit of FIG. 1 is firmware controlled such that the
microprocessor 101, virtual memory management unit 103, cache memory 107
and glue logic 105 each are controlled by microoperations from
microinstructions contained within the control store. As illustrated in
FIG. 1, the control store of the preferred embodiment is a read only
storage, which is distributed throughout the processor such that the
microoperations for the various units are stored in a local read only
storage (ROS) which is close to the logic which utilizes the
microoperations. This distribution of the ROS has the advantage that the
relatively narrow 14-bit address which is used to address the control
store is distributed throughout the central processor, whereas the
relatively wide 104 bit microinstruction is broken into 4 elements so that
each of the local ROS's is close to the logic which utilizes the various
microoperations. Therefore, as can be seen in FIG. 1, microprocessor 101
obtains its 67 bits of microoperations as signals MPROSDT on line 104 from
microprocessor ROS 109. Virtual memory management unit 103 obtains its 16
bits of microoperations as signals VMROSDT on lines 106 from virtual
memory ROS 111. Cache memory 107 obtains its 16 bits of microinstructions
as signals CHROSDT on lines 112 from cache ROS 115, and glue logic 105
obtains its 4 bits of microoperations as signals GLROSDT on lines 108 from
glue ROS 113. In addition, glue logic ROS 113 provides signal ROSPRTY
which is an overall ROS odd parity bit so that each 103 bit
microinstruction has a 104th bit of odd parity associated with it. That
is, the number of bits in the binary ONE state in each 104-bit
microinstruction word in the control store will be an odd number.
The addressing of the control store, which is composed of the four ROS's
109, 111, 113, and 115 is under the control of microprocessor 101 which
calculates the address of the next microinstruction and produces a 14-bit
address as signal ROSADDR on lines 102 which is used to address each of
the ROS's. This 14-bit control store address allows for the addressing of
16K (1K=1024) of 104-bit words in the control store.
By having an odd parity bit (ROSPRTY) as bit 104 associated with each
microinstruction, the central processor unit is able to detect whether the
microinstruction word read from the control store was read without a
single bit error. The detection of read errors as each microinstruction
word is read from the control store is performed by parity
calculator-checker 121 in glue logic 105. If parity calculator-checker 121
detects a difference between the parity calculated for the
microinstruction word and the parity bit contained in the microinstruction
word, it produces a CANCEL signal on line 136 which prevents clock
generator 125 from generating clocking signal CLK4 on line 126. In
addition to producing clock signal CLK4, clock generator 125 produces
clock signals T1, T2, T3 and T4 on lines 128, 130, 132 and 134
respectively. These four clock signals T1 through T4 and CLK4 are used
throughout the central processor to clock various operations within
microprocessor 101, virtual memory management unit 103, cache memory 107
and glue logic 105.
Because the control store is broken into four separate ROS's, with each
separate ROS being located near the logic which its microoperations
control, the calculation of the parity of a microinstruction is also
distributed. Therefore, parity calculator 117 in microprocessor 101
calculates the parity of the 67 bits of microinstruction received form
microprocessor ROS 109. Similarly, parity calculator 119 in virtual memory
management unit 103 calculates the parity of the 16 bits of
microoperations received from virtual memory ROS 111 and parity calculator
123 in cache memory 107 calculates the parity of the 16 bits of
microoperations received from cache ROS 115. Parity calculator 117
produces parity signal MPROSPB on line 118, parity calculator 119 produces
parity signal VMROSPB on line 120, and parity calculator 123 produces
parity signal CHROSPB on line 124. These three parity signals MPROSBP,
VMROSPB and CHROSPB are inputs into parity calculator-checker 121 along
with the four bits of the microoperation received from glue logic ROS 113.
These seven bits along with the odd parity bit ROSPRTY from the
microinstruction words are then used by parity calculator-checker 121 to
compute the total parity of the microinstruction word. If the calculated
parity does not agree with the stored parity, the cancel signal CANCEL on
line 136 is produced. As will be seen below, the CANCEL signal is used to
cancel the execution of the current microinstruction which contains a read
error. The microinstruction is then refetched from the control store and
re-executed.
The method by which the present invention cancels the execution of a
microinstruction that is determined to have a read error in it and the
method by which the microinstruction is reread from the control store and
re-executed will be described with reference to FIGS. 2 and 3 which show
in greater detail the logic of microprocessor 101, parity
calculator-checker 121 and clock generator 125. The operation of the logic
of FIGS. 2 and 3 will also be discussed with reference to FIG. 4 which
shows a timing diagram of various clock timing signals and ROS address and
data signals and read error signals.
As indicated above, the system of the preferred embodiment is designed so
that the major elements within the CPU are firmware controlled by
microoperations with the microprocessor 101 responsible for calculating
the address of the next microinstruction to be fetched, a part of it being
read from microprocessor ROS 109, virtual memory ROS 111, glue logic ROS
113 and cache ROS 115. The CPU is designed so that during the execution of
a first microinstruction the address of the second microinstruction is
presented to each of the ROS's and the reading of the second
microinstruction is initiated during the execution of the first
microinstruction so that the second microinstruction will be available
upon the completion of the execution of the first microinstruction. This
overlapping of the reading of the next microinstruction during the
execution of the current microinstruction is illustrated in FIG. 4 which
shows that the 14-bit control store address signal ROSADDR on lines 102 at
the output of ROS address register 209 is addressing control store
location B during the end of cycle 2 while the contents of ROS data
register 201, the output of which is the 67 firmware bits that control
microprocessor 101 as signals RDROUT on lines 202 contain the contents of
memory location A, which is the current microinstruction being executed
during cycle 2. In FIG. 4, the contents of a memory location is indicated
by putting the memory location address "A", "B", "C", etc. within
parentheses, as seen for signals MPROSDT and RDROUT.
In the preferred embodiment, the time required to execute a
microinstruction by the CPU is broken into four equal time periods: Time
1, Time 2, Time 3 and Time 4. The total time required to execute one
microinstruction is approximately 160 nanoseconds and therefore Time 1
through Time 4 are each 40 nanoseconds long. The CPU logic utilizes timing
signals T1 through T4 associated with Time 1 through Time 4 to clock
various logic elements within the CPU. FIG. 3 shows that a 25 megahertz
oscillator 319 is used to produce the basic clocking signal CLK on line
320. Signal CLK is in the high (binary ONE) state for 20 nonoseconds and
in the low (binary ZERO) state for 20 nanoseconds during each basic clock
period as can be seen in FIG. 4. Signal CLK on line 320 is connected to
the clock (C) input of clock register 327 and to one input of AND gate
323. Clock register 327 is a D-type register of the type enabled by a
binary ZERO at the enable (EN) input and clocks the signals at its D
inputs onto the corresponding Q outputs. The small circle on the inputs,
such as the enable input of register 327, or outputs of the elements in
FIGS. 2 and 3 indicate an inverting input or output, respectively. Since
signal MPRERR at the enable input of clock register 327 is normally in the
binary ZERO state, clock register 327 is normally enabled. Signal MPRERR
becomes a binary ONE and disables the clock and freezes the state of the
CPU by inhibiting the further execution of the microinstructions if an
error is detected within microprocessor 101, but for the purposes of
discussing the present invention it shall be considered to be a binary
ZERO thus continually enabling clock register 327. The binary ONE at the
clear (CLR) and the binary ZERO at the function (F) input of clock
register 327 inhibit the clearing of the register and enable the outputs,
respectively.
Ring counter 325 is a 4-bit ring counter of conventional design. Each
fourth time clocking signal CLKC on line 324 at its clock (C) input
becomes a binary ONE, its output signal, SYNC, on line 326 becomes and
remains a binary ONE until the next time ring counter 325 is clocked by
the transition of the CLKC signal from the binary ZERO to the binary ONE
state. AND gate 323 is normally enabled by signal WAIT at the input of
inverter 321 being a binary ZERO thus making the output of inverter 321,
signal WAIT-bar, the inverse of signal WAIT, a binary ONE. Thus, during
normal operation ring counter 325 will be clocked by each fourth
transition of clocking signal CLK on line 320 from oscillator 319 (see
FIG. 4). Signal WAIT is used within the central processor to indicate when
the clock must be temporarily stalled in order to wait for some event to
happen. Generally, it is used to temporarily stall the CPU until data
becomes available from cache memory 107.
Assuming that there is no need to wait for some event to happen within the
central processor, and therefore signal WAIT is a binary ZERO, signal SYNC
at the D0 input of clock register 327 will become a binary ONE each fourth
time that clock register 327 is clocked by signal CLK on line 320. As is
illustrated in FIG. 4, each fourth basic clock period when signal SYNC at
the D0 input of clock register 327 is a binary ONE, the clocking of the
register by signal CLK becoming a binary ONE will result in the Q0 output
on line 340, signal T2, becoming a binary ONE. Signal T2 remains in the
binary ONE state for one basic clock period (one cycle of signal CLK).
Because signal T2 on line 340 is connected to the D1 input of clock
register 327, the next time that the clock register 327 is clocked, its
corresponding Q1 output will result in signal T3 on line 342 becoming a
binary ONE and remaining a binary ONE for one basic clock period as shown
in FIG. 4. Signal T3 on line 342 is connected to the D2 input of clock
register 327 resulting in signal T4 on line 344 at the Q2 output of clock
register 327 becoming a binary ONE the next time the clock register is
clocked by signal CLK becoming a binary ONE. Signal T4 will remain a
binary ONE for one clock period as shown in FIG. 4 and as an input to the
D3 input of clock register 327 will result in signal T1 on line 346
becoming a binary ONE the next time clock register 327 is clocked by
signal CLK as shown in FIG. 4. The fourth clocking of clock register 327
by basic clock signal CLK, which results in signal T1 becoming a binary
ONE at the Q3 output of clock register 327, will also result in signal
SYNC at the output of ring counter 325 becoming a binary ONE. Therefore,
when the clock register is being clocked by the beginning of the fifth
basic clock cycle, the T2 signal at the Q0 output of clock register 327
will again become a binary ONE as shown in FIG. 4.
Signal T3 on line 342, in addition to being connected to the D2 input of
clock register 327 to produce timing signal T4, is also connected to one
input of AND gate 331. As long as the CANCEL signal on line 136 is a
binary ZERO, the output of inverter 329, which is signal CANCEL-bar on
line 330, will be a binary ONE thus enabling AND gate 331 so that the
state of its output, signal SETCLK4 on line 332, will be determined by the
state of signal T3. Therefore, unless the CANCEL signal is a binary ONE,
the clocking signal CLK4 on line 348 at the Q4 output of clock register
327 will be the same as the timing signal T4 on line 344. If the cancel
signal becomes a binary ONE, AND gate 331 will be disabled and clock
register 327 will not produce signal CLK4 in the binary ONE state at the
same time that timing signal T4 becomes a binary ONE. This can be seen in
FIG. 4 wherein during the time that the CANCEL signal is in the binary ONE
state, the CLK4 signal remains in the binary ZERO state during the time
that timing signal T4 is in the binary ONE state.
Before discussing how parity calculator-checker 121 produces the CANCEL
signal, the operation of the logic in FIG. 2 will be described in
conjunction with the timing of the various signals shown in FIG. 4. As
described above, the address of the next microinstruction to be read from
the control store is determined by the microprocessor 101. Within
microprocessor 101, the generation of the next ROS address is primarily a
function of next address generation logic 203, which receives as input
some of the bits from the currently executing microinstruction which is
stored in ROS data register 201 and is available as signal RDROUT on lines
202 and by the decoding of the microoperations encoded in the current
microinstruction. The decoding of the microoperations is performed by
microoperation decoder 211. FIG. 4 shows that the 14-bit probable next ROS
address at the output of next address generation logic 203 on lines 204 is
available during Times 2, 3 and 4 (i.e., when signals T2, T3 and T4 are
high, respectively).
In FIG. 4, the shaded areas represent periods during which the state of the
signals are indeterminate. For example, signal PNXROSA, which is the
probable next ROS address, is indeterminate during Times 1. FIG. 4 shows
that during the first microinstruction cycle, signal PNXROSA will contain
the address of control store location A. During the second
microinstruction cycle, PNXROSA contains the address of control store
location B. During the third microinstruction cycle, it contains the
address of control store location C, etc.
As long as there is not a hardware retry condition which is caused by a
microinstruction read error in existence, signal HRDRTRY at the select (S)
of multiplexer 207 will be a binary ZERO and the A inputs will be
connected to the outputs so that its 14-bits next ROS address, signal
NXROSAD on line 208, will follow the potential next ROS address, signal
PNXROSA on line 204. This can be seen in FIG. 4 which shows that sometime
during Time 2, next ROS address signal NXROSAD during the first
microinstruction cycle becomes equal to the address associated with
location A of the control store. If a hardware retry condition exists
which causes signal HRDRTRY to be a binary ONE, the stored next ROS
address, signal SNXROSA on lines 206, at the B inputs of multiplexer 207
are gated onto its output causing signal NXROSAD to be equal to signal
SNXROSA. Thus, during the first cycle of a hardware retry condition, the
next ROS address is taken from stored ROS address register 205 instead of
from the next address generation logic 203.
Stored ROS address register 205 is a D-type register which clocks its
inputs onto its outputs when clocking signal CLKS at its clock (C) input
transitions from the binary ZERO to the binary ONE state. Clocking signal
CLKS on line 330 normally transitions from the binary ZERO to the binary
ONE state at the end of Time 4 as the result of signal T4 at one input of
NAND gate 229 transitioning from the binary ONE to the binary ZERO state.
Clocking signal CLKS will normally transition from the binary ZERO to the
binary ONE state at the end of each Time 4 as long as ROS parity error
signal ROSPERR at the input of inverter 227 remains in the binary ZERO
state indicating that a parity error has not been detected while reading
the currently executing microinstruction from control store memory. As
long as signal ROSPERR remains a binary ZERO, the output of inverter 227
will be a binary ONE thus partially enabling NAND gate 229, thus
permitting the state of clocking signal CLKS to be controlled by timing
signal T4. The storing of the possible next ROS address in stored ROS
address register 205 at the end of Time 4 is illustrated in FIG. 4 which
shows that at the beginning of Time 1 of the second microinstruction
cycle, the possible next ROS address, signal PNXROSA, is clocked into
stored ROS address register 205 resulting in the store next ROS address
signal SNXROSA pointing to location A in the control store.
The next ROS address output by multiplexer 207 on lines 208 is latched into
ROS address register 209 by clocking signal T2 at its clock (C) input. ROS
address register 209 is a transparent type latch which enables its inputs
onto its outputs during the time that the clocking signal is in the binary
ONE state and latches the inputs onto the outputs when the clocking signal
transitions from the binary ONE to the binary ZERO state. This is
illustrated in FIG. 4 which shows that during the first miroinstruction
cycle the ROS address signal ROSADDR points to location A within the
control store during Times 3 and 4 of cycle 1 and Time 1 of cycle 2. FIG.
4 shows that the ROS address is indeterminate during Time 2 and that the
inputs are latched onto the outputs at the end of Time 2.
The 14-bit ROS address ROSADDR on lines 102 is input to the address inputs
of microprocessor ROS 109 to address one of the 16K locations within the
control store. This 14-bit ROS address is also presented to the other
portions of the control store, which are the virtual memory ROS 111, the
glue logic ROS 113, and the cache ROS 115, which are illustrated in FIG. 1
but are not shown in FIG. 2. These ROS's are always read enabled by the
write enable (WE) input being in the binary ZERO state as is shown for
microprocessors ROS 109 in FIG. 2. After the ROS address has been
established at the address inputs of microprocessor ROS 109 for a
sufficient period of time to allow the ROS to read out the addressed
location, the corresponding data becomes available at the data outputs of
the various ROS's, and in particular, 67 bits of ROS data become available
on lines 104 as signal MPROSDT. FIG. 4 shows that the contents of the
address microinstruction location becomes available sometimes during Time
4 and remains available during Time 1. The output of inverter 237 is
connected to the clock (C) input of ROS data register 201 which is a
D-type register. When timing signal T4 at the input of inverter 237
becomes a binary ZERO, its output becomes a binary ONE and clocks ROS data
register 201. Thus, it can be seen in FIG. 4 that at the end of Time 4,
the 67-bit output signal on lines 202, which is signal RDROUT, will be set
equal to the signal MPROSTD, which is at the input of ROS data register
201. Thus, during the second microinstruction cycle in FIG. 4, signal
RDROUT contains the contents of location A of the control store and the
address of location A was presented to the address inputs of the control
store during the previous microinstruction cycle. Thus, it can be seen
that microprocessor 101 generates the address of the next microinstruction
during the time that it is executing a current microinstruction.
The method by which a control store read error is detected and by which the
execution of a microinstruction is cancelled during a retry will now be
discussed with reference to FIGS. 2 and 3 and the timing diagram of FIG.
4. In FIG. 2, parity calculator 117 calculates the parity of the 67 bits
of the microinstruction read from microprocessor ROS 109 by receiving as
inputs signal RDROUT from lines 202. Parity calculator 117 calculates the
parity by performing an exclusive OR of the 67 bits and produces as output
signal MPROSPB on line 118 which will be in the binary ONE state if there
are an odd number of binary ONEs in the 67 bits of ROS data and in the
binary ZERO state if there are an even number of binary ONEs in the 67
bits of ROS data. In FIG. 1, parity calculator 119 performs a similar
parity calculation on the 16 bits of ROS data from virtual memory ROS 111
and produces parity signal VMROSPB on line 120. Parity calculator 123 in
cache 107 performs a similar parity calculation on the 16 bits of ROS data
from cache ROS 115 and produces parity signal CHROSPB on line 124.
Signal MPROSPB on line 118, signal CHROSPB on line 124 and signal VMROSPB
on line 120, along with signal TRAPAA on line 350 are inputs to parity
register 301 as shown in FIG. 3. Parity register 301 is a D-type register
which is clocked when timing signal T2 at its clock (C) input transitions
from the binary ZERO to the binary ONE state at the beginning of Time 2.
The outputs of parity register 301 are enabled by the function (F) input
being held at a binary ZERO. Therefore, at the beginning of each Time 2,
parity register 301 captures the status of its four input signals, three
of which are signals which are functions of the parity of that portion of
the microinstruction word from the control store which is used by its
associated logic. Signals MPROSPAR on line 354, CHROSPAR on line 356 and
MVROSPAR on line 357 at the Q1, Q2 and Q3 outputs of parity register 301
and which correspond to inputs signals MPROSPB, CHROSPB and VMROSPB at the
D1, D2 and D3 inputs, respectively, are used as inputs to parity generator
305. The other inputs to parity generator 305 are the signals output by
ROS data register 303.
ROS data register 303 is a D-type register which clocks the data (D) inputs
onto the outputs (Q) when the signal at the clock (C) inputs transitions
from the binary ZERO to the binary ONE state. ROS data register 303
performs a function similar to that of ROS data register 201 in
microprocessor 101 in that ROS data register 303 is used to hold the
microinstruction bits associated with glue logic 105. These bits are
signal GLROSDT0 through GSROSDT3 on lines 108A through 108D and overall
microinstruction parity bit ROSPRTY on line 110. In addition, a set cancel
next control signal SETCNXT on line 372 is held in ROS data register 303.
These input signals produce the corresponding output signals GLROSD0
through GLROSD3, ROSPART and CANNXT on lines 360, 362, 364 366, 368 and
370, respectively. These signals which are input to parity generator 305
correspond to the four bits of the microinstruction from glue logic ROS
113 which are used to control glue logic 105 and the overall
microinstruction parity bit which is used to make the number of binary ONE
bits within a 104-bit microinstruction an odd number. Signal SETCNXT which
produces signal CANNXT is normally in the binary ZERO state and therefore
does not affect the outcome of the parity generation calculation and
check, but can be used by the system to force the cancelling and retry of
a microinstru | | |
