An interface is connected between an OCIA type port and a mailing system peripheral, such as a weighing cell. The interface comprises an input data circuit, operatively connected to a serial data input line and to an associated input clock line, for receiving serial data input words comprising 8 serial data bits and an end-of-message (EOM) bit. The input circuit converts the serial input words into parallel form and transfers them to a programmable interface controller. The interface also includes an output circuit for transforming parallel output words from the interface controller into serial format. The output circuit is operatively connected to a serial data output line and an output data clock line from the OCIA type port. When an output data word is loaded into the output circuit the output line is forced to a predetermined logical level signalling the port the data is available. The port then provides a series of clock pulses to shift the data word out from the output circuit. When the data word is shifted out from the output circuit the circuit returns the output line to the initial state removing the data available signal. The programmable interface controller is responsive to a series of input words as messages from the OCIA type port. The interface controller is operatively connected to a weighing cell for providing weight and status information, and in response to a particular message, returns a message to the OCIA type port providing weight information and status information. In response to other messages, the programmable interface controller enters certain error routines, clears the interface to initial conditions, or resets the weighing cell to zero. The messages are provided in a predetermined format having header words descriptive of the meassage contents and ending in an error check word. The EOM bit of the error check word is of an opposite logical level from the EOM bit of the other words in a message and so indicates the end of the message.
A mailing machine base includes a docking system for a User Interface Controller (UIC) that provides a feedback signal to the mailing machine based on the presence of the UIC. When the UIC is inserted into a docking connector of the mailing machine, the mailing machine detects the presence of the UIC. A delay circuit within the mailing machine provides a signal to a power control circuit after a predetermined time delay. The power control circuit, based on the signal from the delay circuit, will provide power to the UIC only after the UIC has been securely docked for the full predetermined time delay. When the UIC is removed from the mailing machine, the mailing machine, based on the feedback signal, will quickly remove the power provided to the docking connector. Thus, the mailing machine can remain powered during removal and replacement of the UIC.
A system and method for interfacing external processes to a transaction processing system. An interface system is provided that accepts input messages from external processes wherein in the input messages are to be processed by a transaction processing system. The interface system logs received messages and notifies the transaction processing system that a message has been received for processing. The interface system sends a confirmation to the external process indicating that the message has been received. The interface system periodically examines the status of each message as it is being processed by the transaction processing system. Output status messages indicative of such status are created, stored, and sent to an external destination for informational purposes. Outbound data messages are created, stored and sent to an external application. The interface system is event driven, but includes a monitor subsystem to time the start-up of certain processes at periodic intervals.
The present invention provides a data input/output control device integrating a one-chip microcomputer together with a data transfer device and a processor, the data transfer device being constructed to transmit to and receive from an external apparatus serial data and the processor processing data inputted to the data transfer device and transmitting the processed data to the data transfer device to be further transmitted to the external apparatus, the date input/output control device characterized in that a clock of the data input/output control device for an operation thereof is a transfer clock utilized by the external apparatus and the transfer clock is slower than a clock for the processor. The data input/output control device comprises a controller for controlling the data input and the data output of the data transfer device, a flag holding unit for holding a flag which shows if the data have been inputted to the data transfer device by the processor or the external apparatus, a first synchronization circuit for synchronizing an output from the flag holding unit with the transfer clock, the output being sent to the controller, and a second synchronization circuit for synchronizing the output from the flag holding unit with the clock for the processor.
The invention is directed to a method by which data from a first synchronous subsystem is transmitted to a second synchronous subsystem physically spaced from the first subsystem such that the system clock is skewed relative to the two subsystems. Pursuant to the invention, the transmitted data cycle time is multiple of the common system cycle time and a clock signal is forwarded with the data from the first subsystem to the second subsystem. The clock signal forwarded with the data provides an indication to the second subsystem of the instants of time at which received data changes. The data change instants are used to generate a binary signal that inverts its value at each such instant. The binary signal is transmitted through a synchronizer to produce a logic signal in the second subsystem. The logic signal is utilized to transmit the received data into the second subsystem in synchronization with the clock of the second subsystem.
A transmitting data processor comprises a data processing unit for supplying a predetermined length of data to be transferred and generating a transfer start signal, and a data transferring unit receiving the predetermined length of data to be transferred from the data processing unit and for transferring the predetermined length of data in a serial form to a receiving data processor. The transmitting data processor also includes a busy detector for detecting a busy signal from the receiving data processor, a register for temporarily holding the transfer start signal from the data processing unit, and a start controller associated to the data transferring unit for causing the data transferring unit to stop the transfer of data during the period the busy signal is active and for allowing the data transferring unit to start the transfer of data when the busy signal becomes inactive after the transfer start signal is generated. The receiving data processor includes a data receiving unit for receiving the predetermined length of data transferred from the transmitting data processor, and a data processing unit coupled to the receiving unit for processing the received data and generating a transfer acknowledge signal when it has completed the processing of the received data. The receiving data processor also includes a busy signal generator for generating the above mentioned busy signal in response to completion of reception of the predetermined length of data and making the busy signal inactive when the transfer acknowledge signal is generated.
