A multiple memory display controller provides simultaneous display of overlaid image and graphic data in a computer display system. A video random access memory (RAM) in the display controller stores display data corresponding to graphics to be displayed on the computer display monitor. And a series of dynamic RAMS in the display controller stores display data corresponding to images to be displayed on the computer display monitor. A data mixer receives and mixes signals from the video RAM and one of the dynamic RAMs to form signals which are used to drive the display monitor. The signals provide graphics displayed at one resolution overlaid on images displayed at a different resolution on the monitor. A first-in first-out (FIFO) buffer and rectangle loader provide efficient loading of blocks of display data in the display controller memories.

A computer system includes a processor and bus logic, a decode logic circuit for the processor and bus logic access, a memory subsystem and at least one output port. Writes by the processor and bus logic to an output port also update corresponding location in memory through the decode logic. In one arrangement, a logical "OR" gate enables the memory in response to an output of the decode logic for activating the memory subsystem or an output of the decode logic for activating the output port.

A bidirectional first-in first-out buffer device including on a single chip a single bank FIFO memory array, two bidirectional input/output ports, an input multiplexer for selecting which port to input data from, an output multiplexer for selecting which port to output data to, a byte/word converter for converting input data from a byte format to a word format, a word/byte converter for converting output data from a word format to a byte format, a parity generator/checker for generating parity output signals or confirming parity input signals, a flag generator for generating empty/full and half full flags, and control logic for controlling the direction, format and timing of data flow. The device is packaged in a 52-pin plastic leaded chip carrier package.

An image memory control device is disclosed by which high speed reading processing can be performed without causing a CPU of a computer to have a waiting time and without expanding the system scale. When the CPU tries to perform read access to an image memory, a CPU read mode signal is changed over and a first-in first-out memory controller delivers a read access request to a memory access controller irrespective of presence or absence of read access, and data read in from the image memory are stored into a FIFO memory under the control of the memory controller. Upon read accessing from the computer, the data are transferred from the first-in first-out memory, which assures higher speed operation. Where writing of video data and read/write access of the computer to the image memory are performed by a same system, the FIFO memory is used as a common buffer to them in a time dividing condition by changing over between them.

A frame buffer memory has a random access memory (RAM) for storing pixel data words, each word containing pixel data corresponding to a separate set of a plurality pixels along a horizontal raster line of a screen display. Each word is separately addressed.The RAM is organized into tiles, with each tile comprising an array of pixel data word rows and columns corresponding to a separate rectangular subset of horizontally and vertically contiguous display pixels. The RAM is addressed by sequentially applying row and column addresses. A first subset of the column address determines which pixel word row within each tile is addressed, while and a second subset of the column address determines which pixel word column within each tile is addressed. All other bits of the row and column addresses determine which tile is addressed. Means are provided to selectively increment or decrement the first and second subsets of the column address without changing any other address bits, such that words within a selected tile row or column may be successively addressed allowing rapid reading and writing of sequences of pixel data corresponding to contiguous rows or columns of display pixels. A first-in, first-out buffer, provided to store the sequences of data read from the RAM, also includes a barrel shifter to shift bit positions of the data words so stored to facilitate proper pixel alignment during a horizontal scrolling operation. A logic circuit is provided to rapidly modify sequences of data read from the RAM and stored in the buffer prior to rewriting the data to the RAM thereby allowing rapid alteration of pixel attributes.