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Claims  |
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What is claimed is:
1. In a network wherein data is transferred between a main host computer
and a magnetic tape peripheral unit via a peripheral-controller, wherein
said peripheral-controller is initiated by commands from said host
computer to execute data transfer operations and said
peripheral-controller includes a common control circuit unit for
sequencing microcode instructions and a peripheral dependent circuit unit
for managing said tape peripheral unit, the system for regulating data
transfer operations comprising:
(a) buffer memory means in said peripheral-controller for temporarily
storing blocks of data being transferred, said buffer memory means having
channels of connection to said tape peripheral unit and said host
computer;
(b) status sensing means in said peripheral dependent circuit unit for
providing status signals to said common control circuit for indicating the
number of blocks of data residing in said buffer memory means during each
clock cycle;
(c) signal output means connected to said status sensing means and
functioning to provide said status signals to said common control circuit
unit;
(d) said common control circuit unit including:
(d1) means for generating basic clock cycles;
(d2) means for executing buffer-host data work transfers using said basic
clock cycles;
(d3) means for concurrently executing buffer-peripheral data word transfers
by stealing selected clock cycles of said basic clock cycles;
(d4) wherein said means for executing and said means for concurrently
executing are controlled in response to said status signals.
2. The system of claim 1, wherein said means for executing buffer-host data
word transfers include:
(a) a burst mode data word transfer operation functioning to transfer data
words between said buffer memory means and said host computer at a speed
at least eight times faster than data word transfers between said buffer
memory means and said peripheral tape unit.
3. The system of claim 2, wherein said status sensing means includes:
(a) shift register count means having "X.sub.m " bit positions where a
"true" signal in each bit position represents a full block of N data words
residing in said buffer memory means during that clock cycle, said "true"
signal being incremented/decremented for each block of data words added
to/removed from said buffer memory means;
(b) block counter logic means for incrementing/decrementing said shift
register count means, and including:
(b1) means for counting blocks of data words added to/removed from said
buffer memory means.
4. A system for maximizing the effective rate of data transfer operations
between a host computer and a peripheral tape unit, wherein data transfer
instructions from said host computer are executed by a
peripheral-controller having a data buffer storage means and a
microprocessor means, said system comprising, in combination:
(a) data buffer storage means organized to store data words in multiple
blocks where each block holds N data words;
(b) said data buffer storage means having channels of connections between
said host processor and said peripheral tape unit and functioning to
temporarily store data words-in-transit between said host computer and
said peripheral tape unit;
(c) buffer memory sensing means for providing status data signals to said
microprocessor means, as to the number of blocks of data words residing in
said buffer storage means during each basic clock cycle;
(d) said microprocessor means for selecting and controlling data transfer
operation cycle and including:
(d1) means for generating basic clock cycles;
(d2) means for sensing said status data signals;
(d3) means for addressing data words in said buffer storage means;
(d4) means for concurrently executing Read/Write data transfer cycles
between said buffer storage means and said host processor, and between
said buffer storage means and said peripheral tape unit.
5. The system of claim 4, wherein said microprocessor means includes:
(a) Automatic Read/Write logic means for executing data word transfer of
blocks of data between said buffer storage means and said peripheral tape
unit without interruption to said microprocessor means wherein selected
basic clock cycles are stolen from buffer-host transfers to be used for
buffer-peripheral tape transfers.
6. In a system using a peripheral controller providing for word transfers
between a host computer and buffer memory, and for concurrent word
transfers between a peripheral tape unit and buffer memory, and operating
to monitor the number of blocks of data words in said buffer memory and to
provide control signals to a microprocessor means in said peripheral
controller for maximizing the rate of data transfers and minimizing the
occurrence of incomplete transfer cycles, the combination comprising:
(a) a buffer memory organized to store blocks of "N words" each of data and
including:
(a1) first channel means for transferring data between said buffer memory
and said host computer;
(a2) second channel means for transferring data between said buffer memory
and said peripheral tape unit;
(b) block counter register means receiving block count
increment/decrement/no change signals from a block counter logic unit and
including:
(b1) means to store status signals representing the number of blocks of
data words residing in said buffer memory at each clock cycle;
(b2) means to communicate said status signals to said microprocessor means;
(c) said block counter logic means including:
(c1) means to count the number of data words transferred between said
buffer memory and said host computer for each selected transfer cycle, via
receipt of a system data block signal from an address register means;
(c2) means to count the number of data words transferred between said
buffer memory and said peripheral tape unit for each selected transfer
cycle, via receipt of a peripheral data block signal from said address
register means;
(c3) means to sense the condition of each selected transfer cycle as to
being a Read or a Write operation through Read/Write microcode signals
from said microprocessor means;
(c4) means to generate said increment/decrement/no change signal to said
block counter register means;
(d) address register means for receiving buffer memory addresses from said
microprocessor means and including:
(d1) system address register means for sensing the number of data words
transferred between said host computer and said buffer memory, on a
selected transfer cycle, and generating a system data block signal for
each block of N words;
(d2) peripheral address register means for sensing the number of data words
transferred between said buffer memory and said peripheral tape unit on a
selected transfer cycle, and generating a peripheral data block signal for
each block of N words;
(e) microprocessor means for controlling and selecting data transfer cycles
and including:
(e1) means for selecting Read/Write data transfer cycles between said host
and buffer memory or between said peripheral tape unit and buffer memory,
and including means to generate said Read/Write microcode signals to said
block counter logic means;
(e2) means for sensing said status signals in said block counter register
means to enable selection of the optimum data transfer operation;
(e3) means for generating basic clock cycles for enablement of buffer
memory-host computer data transfers;
(e4) means for selectively stealing certain of said basic clock cycles for
enablement of buffer memory-peripheral tape data transfers;
(e5) wherein concurrent data transfers between buffer-host and transfers
between buffer-peripheral may be interleaved.
7. The combination of claim 6 including:
(a) automatic Read/Write logic means, initiated by said microprocessor
means, for controlling data word transfers between said buffer memory and
tape peripheral unit using stolen clock cycles concurrently with data word
transfers occurring between said host and buffer memory.
8. The combination of claim 7 which includes:
(a) automatic incrementing register means for automatically incrementing
said peripheral address register means during operation of said automatic
Read/Write logic means.
9. The combination of claim 8 which includes:
(a) means for testing said block counter register means by simulating said
increment/decrement/no change signals.
10. In a peripheral controller which manages data transfers between a host
computer and a peripheral tape until wherein said peripheral controller
has a buffer memory for temporary storage of data words-in-transit and
provides a rapid burst-mode routine for host-buffer data transfers and
automatic read/write logic control for buffer-peripheral tape data
transfers, said burst routine and automatic logic control occurring
concurrently on an interleaving clock cycle operation, an optimizing
system for monitoring the number, on each clock cycle, of blocks of data
words residing in said buffer memory to provide information for said
peripheral controller in selecting optimum routines for maximizing the
rate of data transfer operations while minimizing the likelihood of
incomplete and erroneous data transfer cycles, said optimizing system
comprising:
(a) buffer memory means having a first communication channel to a host
computer system and a second communication channel to a peripheral tape
unit, and including:
(a1) address bus connection means for receiving addresses from a system
address register and a peripheral address register;
(b) said system address register for temporary storage of buffer addresses
to be accessed in said buffer memory means when data words are being
transferred between said host computer and said buffer memory means, and
including:
(b1) system bus connection means for receiving addresses from a
microprocessor means;
(b2) means to generate a system-carry signal when "N" data words in said
buffer memory means have been addressed;
(c) said peripheral address register for temporary storage of buffer
addresses to be accessed in said buffer memory means when data words are
being transferred between said buffer memory means and said peripheral
tape unit, and including:
(c1) peripheral bus connection means for receiving addresses from said
microprocessor means;
(c2) means to generate a peripheral-carry signal when "N" data words in
said buffer memory means having been addressed;
(d) block counter logic means receiving said system-carry and said
peripheral-carry signals together with a Read/Write signal from said
microprocessor means, said logic means generating, on each clock cycle, a
first and second count logic signal to a gating means;
(e) gating means for generating, on each clock cycle, an up-count signal,
down-count signal, or a non-count signal to a block counter register means
and including:
(e1) means for generating said up-count, down-count or non-count signals
via microcode signals from said microprocessor means in lieu of said block
counter logic means;
(f) said block counter register means having "X.sub.m " bit positions where
a "true" signal in each bit position represents a full block of N data
words as presently residing within said buffer memory means, and wherein
said up-count signal acts to increment the number "X" of true signals in
said bit positions while said down-count signal acts to decrement the
number "X" of true signals in said bit positions;
(g) said microprocessor means generating basic clock cycles and operating
routines for executing
(i) Read/Write data word transfers between said host and said buffer memory
means, and
(ii) Read/Write data word transfers between said buffer memory means and
said peripheral tape unit, said microprocessor means including:
(g1) means to generate buffer memory addresses for transmittal to said
system and said peripheral address registers;
(g2) means to generate Read/Write control signals to said block counter
logic means;
(g3) means to generate up-count, down-count, non-count microcode signals to
said gating means for testing operation of said block counter register
means;
(g4) means to scan said block counter register means to establish the
number "X" of blocks of data words residing in said buffer memory means;
(g5) means for selecting the next appropriate operating routine based on
the value of the said number "X".
11. The system of claim 10 wherein, on a Read operation, when the value of
X is less than 2 (blocks), the said microprocessor means will disconnect
said first communication channel to said host computer to permit it to
service other peripheral controllers.
12. The system of claim 10 wherein, on a Read operation, when the value of
X is "2" or greater, the said microprocessor means will initiate a
connection on said first communication channel to said host computer and
execute a burst mode data transfer operation from said buffer memory means
to said host computer.
13. The system of claim 10 wherein, on a Read operation, when the value of
X is "6", said microprocessor means generates an access error signal to
said host computer.
14. The system of claim 10 wherein, on a Write operation, when the value of
X reaches "6", the said microprocessor means will disconnect said first
communication channel to said host computer to permit it to service other
peripheral controllers.
15. The system of claim 10 wherein, on a Write operation, when the value of
X reaches "1", the said microprocessor means will generate an access error
signal to said host computer. |
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Claims |
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Description |
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FIELD OF THE INVENTION
This invention is related to systems where data transfers are effectuated
between a peripheral terminal unit and a main host computer wherein an
intermediate I/O subsystem is used to perform the housekeeping duties of
the data transfer.
CROSS REFERENCES TO RELATED INVENTIONS
This disclosure relates to the following patent applications:
"System for Regulating Data Transfer Operations", inventors G. Hotchkin, J.
V. Sheth and D. J. Mortensen, filed Dec. 7, 1982 as U.S. Ser. No. 447,389.
"Burst Mode Data Block Transfer System", inventors J. V. Sheth and D. J.
Mortensen, filed Jan. 11, 1983 as U.S. Ser. No. 457,178 now U.S. Pat. No.
4,542,457.
"Magnetic Tape-Data Link Processor", inventor J. V. Sheth, filed June 30,
1983, as U.S. Ser. No. 509,582.
"Automatic Write System for Peripheral Controller", inventor J. V. Sheth,
filed June 30, 1983 as U.S. Ser. No. 509,796 now U.S. Pat. No. 4,534,013.
BACKGROUND OF THE INVENTION
A continuing area of developing technology involves the transfer of data
between a main host computer system and one or more peripheral terminal
units. To this end, there has been developed I/O subsystems which are used
to relieve the monitoring and housekeeping problems of the main host
computer and to assume the burden of controlling a peripheral terminal
unit and to monitor control of data transfer operations which occur
between the peripheral terminal unit and the main host computer system.
A particular embodiment of such an I/O subsystem has been developed which
uses peripheral controllers known as data link processors whereby
initiating commands from the main host computer are forwarded to a
peripheral-controller which manages the data transfer operations with one
or more peripheral units. In these systems the main host computer also
provides a "data link word" which identifies each task that has been
initiated for the peripheral-controller. After the completion of a task,
the peripheral-controller will notify the main host system with a
result/descriptor word as to the completion, incompletion or problem
involved in the particular task.
These types of peripheral-controllers have been described in a number of
patents issued to the assignee of the present disclosure and these patents
are included herein by reference as follows:
U.S. Pat. No. 4,106,092 issued Aug. 8, 1978, entitled "Interface System
Providing Interfaces to Central Processing Unit and Modular
Processor-Controllers for an Input-Output Subsystem", inventor D. A.
Millers, II.
U.S. Pat. No. 4,074,352 issued Feb. 14, 1978, entitled "Modular Block Unit
for Input-Output Subsystem", inventors D. J. Cook and D. A. Millers, II.
U.S. Pat. No. 4,162,520 issued July 24, 1979, entitled "Intelligent
Input-Output Interface Control Unit for Input-Output Subsystem", inventors
D. J. Cook and D. A. Millers, II.
U.S. Pat. No. 4,189,769 issued Feb. 19, 1980, entitled "Input-Output
Subsystem For Digital Data Processing System", inventors D. J. Cook and D.
A. Millers, II.
U.S. Pat. No. 4,280,193 issued July 21, 1981, entitled "Data Link Processor
for Magnetic Tape Data Transfer System", inventors K. W. Baun and J. G.
Saunders.
U.S. Pat. No. 4,313,162 issued Jan. 26, 1982, entitled "I/O Subsystem Using
Data Link Processors", inventors K. W. Baun and D. A. Millers, II.
U.S. Pat. No. 4,322,792 issued Mar. 30, 1982, entitled "Common Front-End
Control for a Peripheral Controller Connected to a Computer", inventor K.
W. Baun.
U.S. Pat. No. 4,534,013, issued Aug. 6, 1985, to inventor Jayesh V. Sheth
and entitled "Automatic Write System For Peripheral-Controller".
U.S. Pat. No. 4,390,964, issued June 28, 1983, to inventors Joseph F. Horky
and Ronald J. Dockal and entitled "Input-Output Subsystem Using Card
Reader-Peripheral Controller". This patent discloses the use of a
Distribution Card unit used to connect and disconnect the peripheral
controller (Data Link Processor) to/from a host computer as required to
accommodate data transfer operations.
The above patents, which are included herein by reference, provide a
background understanding of the use of the type of peripheral-controllers
known as "data link processors", DLP, used in a data transfer network
between a main host computer and peripheral terminal unit.
In the above mentioned Baun patent, there was described a
peripheral-controller which was built of modular components consisting of
a common front end control circuit which was of a universal nature for all
types of peripheral controllers and which was connected with a peripheral
dependent board circuit. The peripheral dependent circuit was
particularized to handle the idiosyncrasies of specific peripheral
terminal units.
The present disclosure likewise uses a peripheral-controller (data link
processor) which follows the general pattern of the above described
system, in that the peripheral-controller uses a common control circuit or
common front end which works in coordination with a peripheral dependent
circuit which is particularly suited to handle a specific type of
peripheral terminal unit, such as a Tape Control Unit (TCU) which connects
to one or more magnetic tape units.
SUMMARY OF THE INVENTION
The present invention involves a data transfer network wherein a
peripheral-controller known as a data link processor is used to manage and
control data transfer operations between a peripheral such as a magnetic
tape unit (or a tape control unit) and the main host computer system,
whereby data is transferred rapidly in large blocks, such as a block of
256 words.
The data link processor provides a RAM buffer memory means for temporary
storage of data being transferred between peripheral and host system. In
this case, the RAM buffer is capable of holding at least six blocks or
units of data, each of which consists of 256 words, each word being of 16
bits.
In order to facilitate and control those activities in which (a) data is
sometimes being "shifted into" the RAM buffer memory means from either the
peripheral unit or from the main host computer and (b) the data in the RAM
buffer memory is being "shifted out" either to the magnetic tape unit
peripherals, for example, or to the main host computer, it is necessary
that the peripheral-controller and the system have data which informs it
of the condition of the RAM buffer memory means with regard to the amount
of data residing therein at any given period of time.
Thus, there is disclosed a system for regulating data transfer operations
between host and peripheral whereby a peripheral-controller senses blocks
of data stored in its RAM buffer in order to choose routines for data
transfer appropriate to the data condition of the RAM buffer. The
peripheral-controller makes use of a block counter monitoring system which
will inform the peripheral-controller and the main host system of the
"numerical block status" of data in the RAM buffer memory means.
In particular, the present invention discloses a system whereby the common
front end (common control) circuit uses routines providing microcode
instructions to address registers which access locations in the RAM buffer
memory for the insertion of data or the withdrawal of data. There are two
address registers, one for addresses of data taken from/to the peripheral
unit (peripheral address register) and one for addresses of data (system
address register) which are to be forwarded from/to the main host
computer. The peripheral address register is enhanced by use of an
auxiliary Automatic Incrementing Peripheral Register unit to help
establish buffer memory addresses during buffer-peripheral word transfers
using the system's Automatic Read/Write logic mode.
A block counter logic circuit receives input from the peripheral address
register and the system address register. In addition, a flip-flop output
to the block counter logic circuit indicates the direction of data flow as
being a "Write" (host-to-peripheral) or a "Read" (peripheral-to-Host). The
block counter logic circuit provides two output logic signals which
control a block counter. This enables the block counter to be shifted up
or shifted down so that the internal signal data indicates the number of
blocks of data residing in the RAM buffer memory. Certain parameters may
be set to trigger signal output conditions when the amount of data in the
RAM buffer memory falls below a certain figure.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates the block counter system of the present disclosure which
is used to inform the data transfer system of the status of a buffer
memory means.
FIG. 2 is a system diagram showing the host computer cooperating with a
peripheral-controller in order to control data transfer to and from a
peripheral unit.
FIG. 3 is a drawing showing an eight bit shift register which can be
shifted up or down according to conditions which occur between certain
logic signals and clock signals.
FIG. 4 is a diagram showing how the block counter logic unit of FIG. 1 is
organized to operate during Read or Write operations and the effect of
either shifting up or shifting down the shift register.
FIG. 5A is a schematic drawing illustrating the RAM buffer memory used for
temporary storage of data-in-transit.
FIG. 5B is a chart indicating various "shift" relationships of the buffer
memory block counter with regard to "Read" and "Write" operations.
FIG. 6 is a drawing of the common front end unit which provides a state
machine sequencer for microcode instructions.
FIGS. 7A and 7B combine to show the first card of the peripheral dependent
unit circuitry.
FIG. 8 shows the second card of the peripheral dependent unit circuitry.
FIG. 9 is a detailed block drawing of the block counter logic 33.sub.c of
FIG. 1.
FIG. 10 is a timing diagram showing how the basic clock cooperates with the
S carry and P carry signals to provide the SCR8 or PCR8 signal for 5B.
FIG. 11 is a drawing of a three stage counter used to provide the P carry
or the S carry signal after 256 counts to indicate one full block of data
words have been addressed in the buffer memory.
A "Read" operation takes data from a peripheral magnetic tape unit and
temporarily stores it in a RAM memory buffer for later transfer to the
host system.
A "Write" operation takes data from the main host system for temporary
storage in the RAM buffer memory for subsequent transfer to a selected
magnetic tape unit via a TCU or Tape Control Unit.
GENERAL SYSTEM OPERATION
To initiate an operation, the host system 10, FIG. 2, sends the
peripheral-controller (data link processor 20.sub.t) an I/O descriptor and
also descriptor link words. The term "DLP" will be used to represent the
Data Link Processor (peripheral-controller 20.sub.t). The "I/O descriptor"
specifies the operation to be performed. The descriptor link contains path
selection information and identifies the task to be performed, so that
when a report is later sent back to the main host system 10, the main host
system will be able to recognize what task was involved. After receipt of
the I/O descriptor link, the data link processor (DLP) makes a transition
to one of the following message level interface "states".
(a) Result Descriptor: This state transition indicates that the data link
processor 20.sub.t is returning a result descriptor immediately without
disconnection from the host computer 10. For example, this transition is
used when the DLP detects an error in the I/O descriptor.
(b) DISCONNECT: This state transition indicates that the
peripheral-controller 20.sub.t which is designated as the Magnetic
Tape-Data Link Processor (MT-DLP) cannot accept any more operations at
this time and that the I/O descriptor and the descriptor link were
received without errors. This state also indicates that data transfers or
result descriptor transfers can occur.
(c) IDLE: This state transition indicates that the DLP 20.sub.t can accept
another legal I/O operation immediately and that the I/O descriptor and
the descriptor link were received without errors.
When the operation is completed, the DLP 20.sub.t returns a result
descriptor indicating the status of the operation to the main host system.
If the DLP detects a parity error on the I/O descriptor or the descriptor
link, or if the DLP cannot recognize the I/O descriptor it received, then
the DLP cannot proceed with execution of the operation. In this case, the
DLP returns a one-word result descriptor to the host. In all other cases
the DLP returns a two-word result descriptor.
The data link processor 20.sub.t is a multiple-descriptor data link
processor capable of queuing one I/O descriptor for each magnetic tape
unit to which it is connected. There are certain descriptors (Test/Cancel;
Test/Discontinue; and Test/ID) which are not queued, but which can be
accepted at any time by the DLP. Test/Cancel and Test/Discontinue OPs are
issued against a single magnetic tape unit in a queue dedicated to that
peripheral unit, and require that an I/O descriptor for that particular
magnetic tape unit already be present within the DLP. If an I/O descriptor
is received and violates this rule, the DLP immediately returns a result
descriptor to the host. This result descriptor indicates "descriptor
error" and "incorrect state".
As previously discussed in the referenced patents, the MT-DLP utilizes the
following status states (STC) transitions when "disconnected" from the
host:
STC=3 to STC=1; IDLE to DISCONNECT
indicates that the DLP is attempting to process a queued OP.
STC=1 to STC=3; DISCONNECT to IDLE
indicates that the DLP is prepared to accept a new I/O descriptor.
STC=3 to STC=5; IDLE to SEND DESCRIPTOR LINK
indicates that the DLP is executing an OP, and that the DLP requires access
to the host computer.
STC=1 to STC=5; DISCONNECT to SEND DESCRIPTOR
LINK indicates that the DLP is executing an OP, and that the DLP requires
access to the host computer.
The DLP status states can be represented in a shorthand notation such as
STC=n.
Upon completion of an I/O operation, the data link processor forms and
sends the result descriptor to the host system. This descriptor contains
information sent by the tape control unit 50.sub.tc to the DLP in the
result status word, and also information generated within the DLP. The
result descriptor describes the results of the attempt to execute the
operation desired.
DESCRIPTOR MANAGEMENT
All communications between the DLP 20.sub.t and the host system 10 are
controlled by standard DLP status states as described in the previously
referenced patents. These status states enable information to be
transferred in an orderly manner. When a host computer 10 connects to the
DLP 20.sub.t, the DLP can be in one of two distinct states: (a) ready to
receive a new descriptor, or (b) busy.
When in STC=3 (IDLE), the DLP can accept a new I/O descriptor. When in
STC=1 (DISCONNECT) or in STC=5 (SEND DESCRIPTOR LINK), then the DLP is
busy performing a previously transferred operation.
When the DLP receives an I/O descriptor and descriptor link that does not
require immediate attention, the DLP stores the descriptor in its
descriptor queue. The DLP is then able to receive another I/O descriptor
from the host system.
When the host system 10 "Disconnects" from the DLP 20.sub.t after issuing
one or more queued I/O descriptors, then the DLP initiates a search of its
descriptor queue. This search continues until the DLP finds an I/O
descriptor that needs DLP attention, or until the host "reconnects" to
send additional I/O descriptors. If the DLP finds an I/O descriptor that
requires attention, and if the descriptor specifies neither a Test/Wait
for Unit Available OP, nor a Test/Wait for Unit Not Available OP, then the
DLP verifies that the host is still "disconnected". If these conditions
are met, the DLP goes to STC=1 (DISCONNECT) and initiates execution of the
descriptor. Once the DLP goes to STC=1, then no further I/O descriptors
are accepted from the host until the initiated operation has been
completed and a result descriptor has been returned to the host.
The DLP searches its descriptor queue on a rotational basis. The order for
search is not disturbed by the receipt of one or more new I/O descriptors,
nor by the execution of operations. This means that all queued entries are
taken in turn regardless of DLP activity and all units have equal
priority.
When cleared, the DLP halts all operations in progress with the peripherals
and invalidates all the queued I/O descriptors, and returns to Status
STC=3 (IDLE).
DLP-DATA BUFFERS AND DATA TRANSMISSION
The data buffer 22 (FIGS. 1, 5A, 8) of the DLP provides storage for six
blocks of data which are used in a "cyclic" manner. Each of the six blocks
holds a maximum of 512 bytes (256 words) of data. Data is transferred to
or transferred from the host system one block at a time, via the buffer
22, followed by a longitudinal parity word (LPW). Data is always
transferred in full blocks (512 bytes) except for the final block of data
for a particular operation. This last block can be less than the 512
bytes, as may be required by the particular operation.
As seen in FIG. 1, logic circuitry (to be described hereinafter) is used to
feed information to a block counter 34.sub.c which will continuously
register the number of blocks of data residing in buffer 22 at any given
moment. When certain conditions occur, such as a full buffer, or empty
buffer, or "n" number of blocks, the counter 34.sub.c can set to signal
unit 10.sub.c via the peripheral modifier lines of FIG. 6 or to trigger a
flip-flop 34.sub.e which will signal the common control circuit unit
10.sub.c (FIG. 2) to start routines necessary to either transfer data to
the host 10 (after reconnecting to the host) or to get data from the host
10 to transfer to the buffer 22 (seen in FIG. 1, and FIG. 2); or else the
front end unit 10.sub.c (FIG. 2) can arrange to connect the DLP 20.sub.t
to the peripheral (as tape control unit 50.sub.tc) for receipt of data or
for transmission of data.
During a Write operation, the block counter 34.sub.c (FIGS. 1, 7B) counts
the number of blocks of data received from the host system 10. The data
link processor "disconnects" from the host system once the DLP has
received six blocks of data; or it will disconnect upon receipt of the
"Terminate" command from the host system (a Terminate indicates the "end"
of the Write data for that entire I/O operation). After disconnecting from
the host, the data link processor connects to the peripheral tape control
unit (TCU 50.sub.tc). Once proper connection is established between the
data link processor and the tape subsystem, the data link processor
activates automatic logic which allows the tape control unit 50.sub.tc a
direct access to the DLP RAM buffer 22 for use in data transfers.
After the data link processor has transmitted one block of data to the tape
control unit, the data link processor attempts to "reconnect" to the host
system by means of a "poll request" (as long as the host 10 has not
"terminated" the operation). Once this reconnection is established, the
host transfers additional data to buffer 22 of the data link processor
20.sub.t (FIG. 2). This transfer continues until either the six blocks of
RAM buffer memory 22 are again full (a block which is in the process of
being transferred to the tape control unit is considered full during this
procedure), or until the host 10 sends a "Terminate" command. Data
transfer operations between the data link processor 20.sub.t and the tape
control unit 50.sub.tc continue concurrently (on interleaving cycles) with
the host data transfers occurring between host 10 and DLP 20.sub.t (via
the buffer 22).
If the data link processor 20.sub.t has not successfully reconnected to the
host 10 before the DLP has transmitted, for example, four blocks of data
to the tape control unit 50.sub.tc, the data link processor sets
"emergency request" on the data link interface 20.sub.i, FIG. 1. If the
"emergency request" is not successfully serviced before the DLP has only
one block of data remaining for transmission to the tape control unit, the
data link processor sets a "Block Error" condition by signal from
flip-flop 34.sub.e to circuit 10.sub.c. This is reported to the host
system as a "host access error" in the result descriptor and will be
retried subsequently.
The last block of data for any given I/O operation is transferred to the
tape control unit 50.sub.tc directly under micro-code control. During a
"Read" operation, the data link processor first attempts to connect to the
tape control unit 50.sub.tc. Once a successful connection is accomplished,
the data link processor initiates automatic logic to begin accepting data
from the tape subsystem. Once the data link processor has received two
blocks of data (or once the DLP receives all the data from the operation
if the total length is less than two blocks), the data link processor
attempts to connect to the host using a "poll request". The data link
processor continues to accept tape data while at the same time affecting
this host connection.
If the host does not respond to the "poll request" before four blocks of
data are present in the DLP RAM buffer 22, the data link processor sets
"emergency request" on the data link interface 20.sub.i. If no connection
to the host system is effectuated before all of the six RAM buffers are
filled, then the data link processor sets "host access error" in the
result descriptor.
Once the host system answers a "poll request", the data link processor
20.sub.t starts to send data to the host system 10 (which data came from a
peripheral magnetic tape unit) while at the same time continuing to
receive data from the tape control unit 50.sub.tc. After the host 10, FIG.
2, has received one block of data, the data link processor checks whether
or not two full blocks of data remain to be transferred to the host. If
this is so, the DLP uses a "break enable". If a "break enable" request is
granted, then transmission of the next data buffer to the host continues
to occur. If there are less than two full blocks of data in the RAM buffer
22 (or if the "break enable" is refused), the data link processor
disconnects from the host and waits for two full blocks of data to be
present. If a "break enable" is refused, the data link processor initiates
another "poll request" immediately after disconnection.
When the data link processor has completed data transfer, the tape control
unit 50.sub.tc enters the result phase and sends two words of result
status to the data link processor 20.sub.t. The DLP then incorporates this
information, plus any internal result flags, into the result descriptor
which the DLP then sends to the host.
DESCRIPTION OF PREFERRED EMBODIMENT
Referring to FIG. 2, the overall system diagram is shown whereby a host
computer 10 is connected through an I/O subsystem to a peripheral unit,
here, for illustrative purposes, shown as a tape control unit 50.sub.tc.
This tape control unit (TCU) is used to manage connection to a plurality
of Magnetic Tape Unit (MTU) peripherals. As per previous descriptions in
the above cited patents which were included by reference, the I/O
subsystem may consist of a base module which supports one or more various
types of peripheral-controllers, in addition to other connection and
distribution circuitry such as the distribution control circuit 20.sub.od
and the data link interface 20.sub.i. The peripheral-controller 20.sub.t
is shown in modular form as being composed of a common front end circuit
10.sub.c and a peripheral dependent circuit shown, in this case, as being
composed of two peripheral dependent boards designated 80.sub.p1 and
80.sub.p2.
In this network situation, it is often desired that data from the main host
computer be transferred on to a peripheral unit, such as a magnetic tape
unit, for recording on tape. This would be done via a peripheral tape
control unit TCU such as 50.sub.tc. Likewise, at times it is desired that
data from the magnetic tape unit be passed through the tape control unit
to be read out by the host computer. Thus, data is transferred in a
bidirectional sense, that is, in two directions at various times in the
activities of the network.
The key monitoring and control unit is the data link processor 20.sub.t
which when initiated by specific commands of the host computer will
arrange for the transfer of the desired data in the desired direction.
The RAM buffer 22 (of FIGS. 1, 5A) is used for temporary storage of data
being transferred between peripherals and the main host computer. In the
preferred embodiment, this RAM buffer has the capability of storing at
least six "blocks" of data, each block of which consists of 256 words.
The Magnetic Tape Data Link Processor (MT-DLP) consists of three standard
96-chip multi-layered printed circuit cards that plug into adjacent slots
in the backplane of the base module (FIG. 2). The base module for this
system has been previously described in U.S. Pat. No. 4,322,792 and the
previously referenced patents.
The common front end card 10.sub.c (FIGS. 2, 6) contains:
(a) The master control logic;
(b) 1K.times.17-bit RAM words;
(c) 1K.times.49-bit microcode PROM words which sequence and control the
operation of the DLP;
(d) The interface receivers from the distribution card 20.sub.od and from a
maintenance card in the base module.
In addition to the common front end card 10.sub.c, there are two PDBs or
peripheral dependent boards. These are designated PDB/1 and PDB/2 and are
shown on FIGS. 7A, 7B, 8. These PDBs provide control signals and the
interface to the magnetic tape subsystem.
The PDB/1 card contains: (FIGS. 7A, 7B)
(a) The System and Peripheral RAM Address Registers including an automatic
peripheral incrementing register;
(b) The Binary-BCD Address Decode PROMs;
(c) Op Decode PROMs;
(d) N-Way Microcode Branch Logic;
(e) Burst Counter;
(f) Block Counter;
(g) Host Access Error Logic;
(h) Arithmetic Logic Unit (ALU).
(i) Auto Logic Control/Selection
The second peripheral dependent board card, FIG. 8, designated PDB/2
contains the following:
(a) The Auto Read Logic;
(b) Auto-Write Logic;
(c) Input (Read) and Output (Write) Latches;
(d) A 1K.times.17-bit RAM buffer extension of the Common Front End RAM 22;
(e) Clock Logic for the Tape Control Unit 50.sub.tc ;
(f) Interface Logic for the Tape Control Unit 50.sub.tc.
As discussed in the previously referenced patents, each card in the
peripheral-controller (Data Link Processor) has "foreplane" connectors
through which frontplane cables can interconnect these cards. The cards
are slide-in cards which connect at the backplane connectors into the base
module. The top two foreplane connectors of all three cards of the DLP are
interconnected by means of three-connector, 50-pin foreplane jumper
cables. The common front end is connected to the first board, PDB/1, via
connector and cable and the board PDB/1 is connected to the second board,
PDB/2, via another connector and cable. This is done by means of
two-connector, 50-pin foreplane jumper cables. From the connector on the
second board PDB/2, there is a 50-conductor cable which is connected to an
interface card which plugs into an interface panel board. Connections to
the tape subsystem TCU 50.sub.tc is made from this interface panel board.
COMMON FRONT END CARD (CFE 10c)
In FIG. 6 there is seen a basic block diagram of the common front end card
which has previously been described in U.S. Pat. No. 4,322,792 entitled
"Common Front End Control for a Peripheral Controller Connected to a
Computer", inventor Kenneth W. Baun. The most significant item of the
common front end card | | |
