High-speed switching processor for a burst-switching communications system

We claim:

1. A high-speed switching processor for use in a switch of a burst-switching communications system, a burst being a plurality of bytes, said system including a plurality of switches interconnected by time-division multiplexed communications links, each link having a plurality of frames within each second of time, each frame having a plurality of channels, each channel having communications capacity for the transmission of one byte, a byte being a predetermined number of bits, a bit being one binary digit, said system including a plurality of ports, each port being a component of a switch, said switch including at least one switching processor, a queue sequencer, a character memory, and a channel clock, said character memory and queue sequencer each having a respective bus coupled therewith, said switching processor comprising:

(a) a data/address bus;

(b) control means coupled with said data/address bus for controlling said switching processor, said control means including stored-program memory and execution means, said control means having means for receiving and being responsive to a signal from said channel clock;

(c) jump-address means coupled with said data/address bus and said control means, for generating a jump address based on character-state and channel-state and for transmitting said jump address to said control means, said jump-address means operating substantially in parallel with and independently of said control means;

(d) external-interface means coupled with said data/address bus for providing an interface between said switching processor and said communications links and ports, said external-interface means having the ability to receive a byte in the current channel from a communication link or port, said external-interface means operating substantially in parallel with and independently of said control means;

(e) character-memory interface means coupled with said data/address bus for providing an interface between said switching processor and said character memory, said character-memory interface means having the ability to read or write a byte from said character memory, said character-interface means operating substantially in parallel with and independently of said control means;

(f) queue-sequencer interface means coupled with said data/address bus for providing an interface between said switching processor and said queue sequencer, said queue-sequencer interface means having the ability to receive a buffer address from the queue sequencer, said queue-sequencer interface means operating substantially in parallel with and independently of said control means and said queue sequencer; and

(g) buffer-address means coupled between said queue-sequencer interface means and said character-memory interface means for generating a buffer address based on the channel number, said buffer-address means having the ability to receive said buffer address from said queue-sequencer interface means, said buffer address means operating substantially in parallel with and independently of said control means;

(h) said jump-address means being coupled with said external-interface means and having the ability to receive a byte of a burst from said external-interface means;

(i) said control means having the ability to receive said jump address from said jump-address means and to transfer processing control to the instruction in said stored-program memory located at the address indicated by said jump address.

2. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein the transmission speeds over said communications links are substantially equivalent to the T1 rate or a higher rate.

3. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein a byte is eight bits.

4. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 3 wherein said jump-address means comprises a finite-state machine having character states and channel states.

5. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 4 wherein said character states of said finite state machine comprise clear, flag-found, and data-link escape found.

6. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 5 wherein said channel states of said finite state machine comprise await first header byte, await second header byte, await third header byte, await fourth header byte, process burst, abort burst, await termination sequence, and process control burst.

7. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein said buffer-address means includes a dual-port random-access memory.

8. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein said stored-program memory is a programmable read-only memory having a word length of at least sixty-four bits.

9. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein said system includes a link switch and said switching processor is at least one component of said link switch.

10. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein said communications system includes a hub switch and said switching processor is at least one component of said hub switch.

11. A high-speed switching processor for use in a link switch of a burst-switching communications system, a burst being a plurality of bytes, a byte being a predetermined number of bits, a bit being one binary digit, said system including a link switch having a plurality of ports, each port being a component of said switch, each port being associated with a communications channel, said link switch including at least one switching processor, a queue sequencer, a character memory, and a channel clock, said character memory and queue sequencer each having a respective bus coupled therewith, said switching processor comprising:

(a) a data/address bus;

(b) control means coupled with said data/address bus for controlling said switching processor, said control means including stored-program memory and execution means, said control means having means for receiving and being responsive to a signal from said channel clock;

(c) jump-address means coupled with said data/address bus and said control means, for generating a jump address based on character-state and channel-state and for transmitting said jump address to said control means, said jump-address means operating substantially in parallel with and independently of said control means;

(d) external-interface means coupled with said data/address bus for providing an interface between said switching processor and said ports, said external-interface means having the ability to receive a byte in the current communications channel, said external-interface means operating substantially in parallel with and independently of said control means;

(e) character-memory interface means coupled with said data/address bus for providing an interface between said switching processor and said character memory, said character-memory interface means having the ability to read or write a byte from said character memory, said character-interface means operating substantially in parallel with and independently of said control means;

(f) queue-sequencer interface means coupled with said data/address bus for providing an interface between said switching processor and said queue sequencer, said queue-sequencer interface means having the ability to receive a buffer address from the queue sequencer, said queue-sequencer interface means operating substantially in parallel with and independently of said control means and said queue sequencer; and

(g) buffer-address means coupled between said queue-sequencer interface means and said character-memory interface means for generating a buffer address based on the channel number, said buffer-address means having the ability to receive said buffer address from said queue-sequencer interface means, said buffer address means operating substantially in parallel with and independently of said control means;

(h) said jump-address means being coupled with said external-interface means and having the ability to receive a byte of a burst from said external-interface means;

(i) said control means having the ability to receive said jump address from said jump-address means and to transfer processing control to the instruction in said stored-program memory located at the address indicated by said jump address.

12. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 11 wherein a byte is eight bits.

13. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 12 wherein said jump-address means comprises a finite-state machine having character states and channel states.

14. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 13 wherein said character states of said finite state machine comprise clear, flag-found, and data-link escape found.

15. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 14 wherein said channel states of said finite state machine comprise await first header byte, await second header byte, await third header byte, await fourth header byte, process burst, abort burst, await termination sequence, and process control burst.

16. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 11 wherein said buffer-address means includes a dual-port random-access memory.

17. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 11 wherein said stored-program memory is a programmable read-only memory having a word length of at least sixty-four bits.

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CROSS-REFERENCES TO RELATED APPLICATIONS

U.S. patent application Ser. Nos. 762,593, 762,594, 762,641, 762,589, 762,642, 762,588, and 762,591, filed concurrently herewith and assigned to the same assignee hereof, contain related subject matter.

TECHNICAL FIELD

This invention relates to communications switching systems and their components providing fully integrated voice and data services. In particular, the invention relates to high-speed processors employed in integrated switches.

BACKGROUND OF THE INVENTION

Communications users, particularly telecommunications users, have required ever-increasing ranges of information transport. In the traditional telephone network, voice signals were transmitted and switched through the network in analog form. Because of economies in certain types of transmission media, voice signals were digitized for transmission purposes. Time-division multiplexing of digital voice signals was the most economical way to utilize the wire-based transmission plant of the telephone network.

With the advent of data processing and distributed data processing systems, a need arose for the transmission of data over communications links and through the telephone network. For purposes herein, "data communications" is broadly defined as any information transmitted through a digital communications network other than digitized voice signals. Currently, the most common type of data communications is alphanumerical data, i.e., text or numerical data. Future communications requirements include the ability to carry image and video communications in substantial proportions. Image communications is the transmission of a still picture or motionless object. Facsimile transmission, presently the most common form of image communications, is the transmission of the image of a block or page of information rather than transmission of the digital representations of the letters or characters which comprise the block or page. Video transmission adds motion to image transmission. It can range from transmission of full motion color television signals to freeze-frame video, which is a series of sequential still images. As image and video communications become more prevalent, the demand for bandwidth will increase dramatically. No doubt, there will be even greater communications demands in the future, both as to diversity of services and traffic capacities.

It is well settled that digital time-division multiplexed transmission is preferred for both voice and data communications for a number of reasons not the least of which are the substantial economies realizable from digital multiplexing. Digital multiplexing can occur between communications of the same type, such as interleaving a plurality of voice conversations onto a single pair of wires. A form of multiplexing can also occur between communications of different types, such as inserting data communications into detectable silence periods in voice communications. Such detectable silence periods may occur while one conversant is listening or in gaps between words or syllables of a speaker. Multiplexing is particularly suited to adapting to variable bandwidth demands which result from the inherently "bursty" nature of most voice and data communications. Thus, integration of voice and data is spurred by the substantial economies of digital multiplexing and the growing diversity of services.

A digital communications network or system is said to be "integrated" or to provide "integrated services" if the network or system has the capacity to transmit voice and data communications through common equipment and facilities. An attribute of integrated communications systems is the use of intelligent processors at various points in the network for control purposes. Control is "distributed" or "dispersed" if the overall network control emanates from multiple geographical points, each point using local information or information provided by distant points via the network itself. Thus, the intelligence in a distributed control network is dispersed throughout the geographical area being served. In particular, a switching decision which needs to be made by a local processor can be made with information immediately available to the local processor. In large communications systems, distributed control generally improves efficiency since the intelligence required to route local traffic is nearby. Distributed control also enhances survivability since a local portion of the system, being self-controlled, will remain operable in the event a distant control point should be out of service.

With the ever-increasing demand for transmission bandwidth, it is axiomatic that higher bit rates will be employed over communications links in the future. On the Bell System T1-carrier, of which millions of miles are already installed, a communications link carries 1.544 million bits per second. Links with substantially higher bit rates are feasible even with current technology. The provision of integrated services over high-speed communications links will require new methods, procedures, and protocols governing information transport through the network. In particular, additional bandwidth required by the system for routing and administration, i.e., the "overhead," should be minimized while permitting reasonable flexibility within the network to adapt to changing circumstances. Integrated switching apparatus should be capable of transmitting and routing information at T1 rates and higher, so that optimal channel utilization can be achieved.

Communications systems planners, and in particular telecommunications systems planners, seek high-speed processors for use in switches such that communications links may support integrated services at the T1 transmission rate (or the equivalent) and even faster rates. Such high-speed processors should have other features, such as low cost, ease of maintenance, high suitability for implementation in very-large scale integration technology, etc. It would substantially advance the state of the communications art if such a high-speed processor were available.

DISCLOSURE OF THE INVENTION

It is, therefore, an object of the invention to obviate the deficiencies in the existing art and to make a significant new contribution to the field of communications systems.

It is an object of the invention to provide a communications system having fully integrated voice and data services.

An object of the invention is to provide a communications system employing high-speed communications links, such links having bit rates of T1 or higher.

It is an object of the invention to provide a communications system having highly distributed control and equipment.

An object of the invention is to provide a communications system wherein the control functions are administered entirely through the transmission network; where reallocation of control capacity may be achieved entirely through the transmission network, flexibly, and with virtually no disruption of user services; and where in the event of a failure of a control processor, the responsibilities of the failed processor may be reassigned to one or more surviving control processors.

Another object of the invention is to provide an integrated communications system which makes efficient use of the copper-wire plants of existing telephone networks.

It is an object of the invention to provide methods of information transport within a communications system which require minimal routing and administrative overhead while permitting adequate network flexibility to adapt to changing circumstances.

An object of the invention is to provide an integrated communications system which features low-cost modular components with highly redundant circuits well suited for implementation in very large scale integration technology.

It is an object of the invention to provide an integrated communications system which has the capability to transport voice communications without subscriber-perceptible distortion or delay except possibly under overload conditions.

An object of the invention is to provide a communications system having the capability within each switching node to allocate bandwidth dynamically, i.e., within the current communications channel, and thereby to maximize bandwidth utilization throughout the system.

It is an object of the invention to provide methods of information transport within a communications system which have the capability of handling bursty information, i.e., digital messages of varying length, in a highly efficient manner.

An object of the invention is to provide a link switch which may be employed in a communications system, such link switch having an embodiment which is relatively small and inexpensive whereby it may be highly dispersed geographically and, if desirable, located nearby or on subscriber premises.

It is an object of the invention to provide a hub switch which may be employed in a communications system, such hub switch being a high-speed high-capacity switch which may be located at points of high concentration in the system.

An object of the invention is to provide a high-speed switching processor which may be embodied as a component or as several components in a link switch and/or hub switch of a communications system.

It is an object of the invention to provide a high-speed queue sequencer which may be employed in some embodiments of a communications system as a component in a link switch and/or hub switch.

An object of the invention is to provide a communications system having the capability of providing digital communications from origin port to destination port whereby possible noise interference will be substantially reduced, ease of maintenance improved, and security and privacy enhanced, particularly in the case where the origin port and/or destination port is located on user premises.

It is an object of the invention to provide an integrated communications system wherein the transmission rates received at the ports for bursts containing digitized voice are approximately equal to burst transmission rates over communications links, so that speed buffering of voice bursts within link switches is not required.

It is another object of the invention to provide an intelligent port circuit for a link switch, such port circuit having a high degree of control intelligence whereby the distributed control feature of a communications system may be enhanced when the port circuit is remotely located.

An object of the invention is to provide a port circuit for a link switch which may be located in the vicinity of the subscriber, on the subscriber's premises, or within end-user equipment, such that call or message propagation capacity exists at the hub-switch level, link-switch level, and even at the end-user equipment level, if desired.

It is another object of the invention to provide a port circuit for a link switch, such port circuit having a loop-back testing capability, whereby components of a burst switching system may be remotely monitored for operability including components of the port circuit itself.

An object of the invention is to provide a method of call set-up and take-down in a telephone communications system.

It is another object of the invention to provide a highly distributed control architecture for a communications system in which control capacity can be added or deleted incrementally with virtually no disruption in user services.

These objects are accomplished, in one aspect of the invention, by the provision of a high-speed switching processor for use in a switch of a burst-switching communications system. In such system, a burst is a plurality of bytes which may represent, for example, a block of data or a spurt of voice energy as sensed by silence/voice detectors. The system includes a plurality of switches interconnected by time-division multiplexed communications links. Each communication link has a plurality of frames within each second of time. Each frame has a plurality of channels. Each channel has communications capacity for the transmission of one byte. A byte is a predetermined number of bits, a bit being one binary digit. In a preferred embodiment of the invention, a byte is eight bits, e.g., as with an ASCII character.

The system also includes a plurality of ports, each port being a component of a switch. A switch includes at least one switching processor, a queue sequencer, a character memory, and a channel clock. The character memory and queue sequencer each has a respective bus coupled therewith.

The switching processor comprises a data/address bus. Control means are coupled with the data/address bus for controlling the switching processor. The control means include stored-program memory and execution means. The control means have means for receiving and being responsive to a signal from the channel clock.

Jump-address means are coupled with the data-address bus and control means. The function of the jump-address means is to generate a jump address based on character-state and channel-state and to transmit the jump address to the control means. The jump-address means operates substantially in parallel with and independently of the control means.

External-interface means are coupled with the data/address bus for providing an interface between the switching processor and the communications links and ports. The external-interface means has the ability to receive a byte in the current channel from a communications link or port. The external-interface means operates substantially in parallel with and independently of the control means.

Character-memory interface means are coupled with the data/address bus for providing an interface between the switching processor and the character memory. The character-memory interface means have the ability to read or write a byte from the character memory. The character-interface means have the ability to operate substantially in parallel with and independently of the control means.

Queue-sequencer interface means are coupled with the data/address bus for providing an interface between the switching processor and the queue sequencer. The queue-sequencer interface means have the ability to receive a buffer address from the queue sequencer. The queue-sequencer interface means operate substantially in parallel with and independently of the control means and queue sequencer.

Buffer-address means are coupled with the queue-sequencer interface means and the character-memory interface means for generating a buffer address based on the channel number. The buffer address means has the ability to receive the buffer address from the queue-sequencer interface means. The buffer address means operate substantially in parallel with and independently of the control means.

The jump-address means are coupled with the external-interface means. The jump-address means have the ability to receive a byte of a burst from the external-interface means.

The control means have the ability to receive the jump address from the jump-address means and to transfer processing control to the instruction in the stored-program memory located at the address indicated by the jump address.

In one embodiment of the invention, the burst-switching communications system includes a link switch and the switching processor is at least one component of the link switch. In another embodiment of the invention, the system includes a hub switch and the switching processor is at least one component of the hub switch.

In yet another aspect of the invention, the jump-address means includes a finite state machine having character states and channel states.

Thus, there is provided a high-speed switching processor which, with appropriate firmware or software modification, may be employed as one or more components of a link and/or hub switch. The switching processor will meet the growing communications needs of the present and foreseeable future. This processor incorporates many features and advantages which will be explained in greater detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an embodiment of a burst-switching system.

FIG. 2 shows a preferred embodiment of the digital format of a burst.

FIG. 3 is a block diagram of a link switch in accordance with the invention.

FIG. 3A illustrates the four types of bursts in transit processed by a link switch.

FIG. 3B illustrates a typical prior art parallel priority-resolving circuit which may be used in various embodiments of the invention.

FIG. 4 is a block diagram of a hub switch showing, in particular, the coupling between the switching units of the hub switch with link groups.

FIG. 5 is a block diagram of a hub switch in accordance with the invention.

FIG. 6 is a block diagram of an alternate embodiment of a link switch showing a digital multiplexer coupled between the input and output port processors and twenty-four end-user instruments.

FIG. 7 shows the format of a dynamic buffer containing a portion of a burst in the central memory of a link switch.

FIG. 8 diagrammatically illustrates the linkages between buffers for three bursts on a queue within a link switch.

FIGS. 9A and 9B each show a buffer within character memory of a link switch at two different times in the processing of a burst through the link switch in order to illustrate the input and output indices of the buffer.

FIG. 10 illustrates the flow of four bursts through the input and output processors and character memory of a link switch.

FIGS. 11A through 11E show the linkages between the input and output processors and the queues and buffers in the central memory of a link switch for the various stages in the processing of a burst through a link switch from the time of arrival of the first byte to the time of transmission of the last byte.

FIGS. 12A and 12B illustrate the assignments of bursts to output channels within a link switch in the presence of contention for output channels.

FIG. 13 is a pictorial showing a preferred format of a burst including particular fields within the four header bytes.

FIG. 14 is a table summarizing the data-link escape procedure in accordance with the invention.

FIG. 15 is a schematic representation of a hub switch employed in a burst-switching network.

FIG. 16 is a schematic representation of a single switching unit of the hub switch of FIG. 15.

FIG. 17 shows a block diagram of a hub switching element of the switching unit illustrated in FIG. 16.

FIG. 18 is a diagram illustrating the relationships between hub channels and hub ring circulation periods during a time-division multiplexed hub frame.

FIG. 19 is a diagram illustrating the format of digital burst signals processed by the hub switch.

FIG. 20 is a table summarizing the operations of a switching unit of a hub switch.

FIG. 21 contains a block diagram of a typical link switch showing the queue sequencer and various embodiments, or firmware variants, of the switching processor.

FIG. 22 is a block diagram of the architecture of the basic switching processor.

FIG. 23 is a character state diagram for the finite state machine of the switching processor showing three states.

FIG. 24 is a channel state diagram for the finite state machine of the switching processor showing eight states.

FIG. 25 is a block diagram of the architecture of a queue sequencer in accordance with the invention.

FIG. 25A is a block diagram of an interface circuit employing handshaking logic which, with appropriate adaptation, may be used as any of the interfaces in the switching processor or queue sequencer.

FIG. 26 is a diagram showing the microcode format of the queue sequencer.

FIG. 27 is a diagram showing the microcode format of the switching processor.

FIG. 28 shows the memory configuration of the queue sequencer.

FIG. 29 shows the memory configuration of the switching processor.

FIG. 30 is a functional flowchart for the input processors of a link switch.

FIG. 31 is a functional flowchart for the output processors of a link switch.

FIG. 32.is a block diagram of a port circuit for an analog line which may be employed as a component of a link switch as shown in FIGS. 3 and 6.

FIG. 33 is a block diagram illustrating service sets and the hierarchy of service providers in a typical control architecture for a burst-switching system.

FIG. 34 is a diagram outlining the steps executed by various control processors required to set up a simple call in a burst-switching telephone communications system, such call originating at port X and terminating at port Y of the system.

FIG. 35 illustrates certain control bursts transmitted between control processors in a typical burst-switching control architecture, the illustrated con