Liquid crystal matrix display panel drive method

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BACKGROUND OF THE INVENTION

The present invention relates to a method of driving a liquid crystal matrix display panel, and is particularly directed towards a drive method for a liquid crystal matrix display panel having a large number of display elements, suitable for use as a display terminal in data processing equipment. Such a display is utilized for patterns which represent characters, numerals or graphics (e.g. charts, etc) and which are generally held static on the display screen, or move relatively slowly across the screen. Thus, the patterns produced by such a display will in general remain static during a large number of successive frame intervals (with all of the rows of elements of the display being successively scanned during each frame interval). For ease of description, it will be assumed in the following that each display element of a liquid crystal matrix display panel can attain only an ON and an OFF state, and that the conductors connected to respective rows of display elements, which are successively scanned by drive signal pulses of fixed amplitude (generally referred to as common drive signals), are aligned horizontally and will be referred to as common conductors, while the vertically arrayed conductors which are connected to respective columns of display elements and are driven by data-dependent signals (generally referred to as segment drive signals) will be referred to as segment conductors. It will also be assumed that the display is of the type in which a display element is set in the ON state, to appear dark in color against a background of light-colored OFF state display elements, by application of an RMS level of voltage to the display element of sufficiently high value. The invention is however not limited to liquid crystal displays of the latter type. All of the rows of display elements are successively scanned by the common drive signals during each of successive frame intervals.

As the number of display elements of a liquid crystal matrix display panel is increased, it is found that the display quality deteriorates. Specifically, a reduction of contrast occurs, i.e. the most completely "black" level of display cannot be attained. This is due to various factors, the most important of which are the effects of increased resistance of the conductors which supply drive signals to the display elements, as the size of the display matrix is increased, in conjunction with increased display element capacitance which must be charged and discharged by drive signals applied over those conductors, together with reduction of the duty o5 ratio for which each display element is driven. The present invention is directed towards a further problem which has arisen in recent years with the development of liquid crystal matrix display panels having a large area and a very high display element density, e.g. having 100 rows of display elements or more. This problem is manifested as display contrast irregularity, i.e. the coloration of dark-state and light-state areas of the display is not uniform over the entire display, but is pattern-dependent. For example, in a column of display elements containing a number of successively adjacent display elements which are all driven to the ON (i.e. dark) state, the degree of dark-state density attained by the ON state display elements will be higher (and the OFF state display elements will appear darker) than in the case of an ON state display element in a column in which a number of display elements are successively set in the ON and OFF states in an alternating manner. This effect is due to the fact that, although each display element is periodically addressed to be driven into the ON state or OFF state by voltages applied simultaneously to the corresponding X and Y-direction conductors, the effective RMS value of drive voltage applied to a display element will be affected by the states of other display elements driven by the same common conductor. For each display element, during the nonselection portion of each frame interval (i.e. all of the frame interval other than the portion in which that display element is addressed), a drive signal will be applied which will vary in waveform in accordance with the display states of the other display elements in the same column. If this drive signal contains a substantial high-frequency component then this will be effectively blocked by the resistive impedance of the long, narrow and transparent (hence extremely thin) drive conductors, in combination with the capacitances of the display elements, and so does not significantly affect the effective drive voltage applied to each display element of that column. However if the drive signal contains a large low frequency component, then this will be less affected by the latter resistance-capacitance blocking effect, and will result in a higher RMS drive voltage being applied to each display element driven by that segment conductor. As a result very conspicuous effects, such as vertical stripes of varying density in the (light color) background areas will appear on the display, which will move in accordance with changes in the display pattern.

This problem of pattern-dependent display contrast variation is increased as the display element density and the number of display elements is increased, since the increased display element density will necessitate reduction of drive conductor cross-sectional area and hence increased conductor resistance, while resistance will be further increased by the greater lengths of the common conductors and segment conductors as the number of display elements in the display is increased, while the amount of display element capacitance connected to each drive conductor will also increase proportionately.

Methods of overcoming this problem have been proposed hitherto, as described hereinafter, but these have only proven partially successful. One such proposal has been made in a paper entitled "SID Japan Display '83--the 3d International Display Research Conference Post-Deadline Papers PD5". However as described hereinafter, this proposed method is not effective for all display patterns.

SUMMARY OF THE INVENTION

With a drive method according to the present invention, for any adjacent pair of display elements arrayed along the same display column, each of four different modes of drive voltage polarity alternation is applied M times (where M is an integer) during every 4M successive frame intervals, in the pair of successive intervals in each frame during which these two elements are successively addressed. These modes are referred to as polarity alternation sub-sequences in the following, and consist of a sub-sequence in which both of the display elements are driven with a positive polarity during their respective selection intervals within a frame interval, a sub-sequence in which a first one of the elements is driven with a negative and the other with a positive polarity, a sub-sequence in which the first element is drive with a positive and the other with a negative polarity, and a sub-sequence in which both of the display elements are driven with a negative drive voltage polarity.

The value of M is preferably made equal to 2, in which case four different sequences of polarity alternation of the drive voltage applied during a frame interval to each pair of adjacent display elements along each display column occur during any four consecutive frame intervals. As a result, irrespective of which of the 4 possible display patterns of any (column oriented) adjacent pair of display elements is designated by the display data, spurious drive signals applied to every other element in the same column as a result of driving that pair of display elements will produce an effect which is independent of the display pattern formed by that adjacent pair of elements, since the average number of polarity transitions of such spurious drive signals (averaged over four or more successive frame intervals) will be constant. Since every pattern which can be produced by a column of display elements containing K pairs of mutually adjacent elements must consist of K combinations of the four possible display patterns which can be produced by each pair of mutually adjacent elements, this method ensures that the pattern-dependent interference effects described above can be eliminated.

The method of the present invention enables pattern-dependent variations in the "dark" and "light" states of display elements to be eliminated, even in the case of a panel having a large number of elements and a high element density.

Utilizing the method of the present invention, "flickering" variation of display pattern density is eliminated if it is ensured that the duration of each cycle interval is shorter than the response time of the liquid crystal, i.e. the maximum time interval for which a variation in drive voltage level applied to a display element will produce no visually perceptible change in display element coloration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified plan view of part of a liquid or mat display panel;

FIGS. 2A and 2B are diagrams to show the relationship between common and segment drive signal levels during a row selection interval and the resultant drive voltage applied to the corresponding addressed d element;

FIGS. 2C and 2D illustrate the drive voltage waveforms applied to a display element addressed during a row selection interval R.sub.N, for two different display patterns;

FIG. 3 shows drive voltage waveforms for a prior art method of driving a liquid crystal matrix display panel, whereby the drive voltage applied to each display element is inverted once in each row selection interval;

FIG. 4A shows drive voltage waveforms for another prior art method of driving a liquid crystal matrix display panel, whereby the drive voltage applied to each display element is inverted in successive scanning frame intervals, for the case of a display element within a column of display elements in alternating dark and light states;

FIG. 4B shows drive voltage waveforms for the method of FIG. 2B, for the case of a display element within a column of display elements which are all driven to the dark display state;

FIGS. 5A and 5B are diagrams illustrating contrast irregularity produced by a prior art drive method for the case of a pattern representing the letter F being displayed by a liquid crystal matrix display panel;

FIGS. 6, and 7 are diagrams illustrating drive voltage polarity alternation sub-sequences, for assistance in describing the basic concepts of the present invention;

FIGS. 8A, 8B and 8C are diagrams illustrating drive voltage polarity alternation sequences for embodiments of the present invention, for the case of a cycle interval value of 4 frame intervals being utilized;

FIG. 9 is a diagram illustrating drive voltage polarity alternation sequences for an embodiment of the present invention in which a cycle interval value of 8 frame intervals is utilized;

FIGS. 10A, 10B is a block circuit diagram of a a liquid crystal matrix display panel with associated drive circuits and art control circuit;

FIGS. 11A and 11B are timing charts to illustrate the operatio of the block circuit diagram of FIG. 10;

FIG. 12 is a timing chart to illustrate a prior art drive method as applied to the liquid crystal matrix display panel of FIG. 10;

FIGS. 13 and 14 timing charts to illustrate the application of an embodiment of the method of the present invention to the display system of FIG. 10;

FIG. 15 is a diagram for illustrating the manner in which display pattern dependency of the frequency components in a segment conductor drive signal is substantially entirely eliminated by the method of the present invention, for the case of a cycle interval of 4 frame intervals;

FIGS. 16A and 16B are diagrams for illustrating the manner in which pattern dependency of drive signal frequency components arises with a proposed prior art method having similar objectives to the present invention;

FIGS. 17A and 17B are diagrams for illustrating how pattern dependency of display contrast will arise with a drive method employing successive drive voltage polarity alternation, which does not meet the essential requirements set by the present invention;

FIG. 18 is a general block circuit diagram to illustrate how the drive system of FIG. 10 can be adapted to utilize the drive method of the present invention;

FIG. 19 is a circuit diagram of a suitable power supply arrangement for the drive system of FIG. 10, when this system is adapted for use with the method of the present

FIG. 20 is a circuit diagram of a specific circuit implementation of a polarity control signal generating circuit for use in applying the method of the present invention to the block diagram of FIG. 10, and;

FIG. 21 is a timing chart for illustrating the operation of the circuit of FIG. 20.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 illustrates the basic elements of a liquid crystal matrix display panel, in very simplified form. A set of horizontally oriented drive conductors 12, referred to in the following as common conductors, are successively scanned by selection voltage signals, generally referred to as common drive signals. The time interval during which a common conductor is addressed by a common drive signal will be referred to as a row selection interval, and the duration of one row selection interval as 1H. The time taken to completely scan all of the common conductors will be referred to as a frame interval, i.e. each display element in a column of the matrix array will be addressed during a 1H interval, once in every frame interval. A set of vertically oriented drive conductors 14, referred to in the following as segment conductors, receive data drive signals, generally referred to as segment drive signals. Liquid crystal is sandwiched between these two sets of drive conductors, with display elements being thereby driven at the intersections of the conductors, e.g. display elements 16a, 16b, 16c, . . . in FIG. 1 are driven into display states which are determined by the level of the segment drive signal V.sub.SEG applied to common conductor 15 during the intervals in which the corresponding common conductors are addressed. The manner in which each display element is addressed by the common and segment drive signals is illustrated in FIGS. 2A and 2B. In FIG. 2A, the drive voltage V.sub.LC is shown for a display element which is addressed during a row selection interval R.sub.N by the corresponding common drive signal V.sub.COM. As shown signal V.sub.COM rises from the zero (0V) level to the +V.sub.H level during row selection interval R.sub.N. If this display element is to be set in the ON state, then the segment drive signal V.sub.SEG goes to the level -V.sub.L during row selection interval R.sub.N As a result, a drive voltage V.sub.LC of level (V.sub.H +V.sub.L) is developed across this display element during the R.sub.N row selection interval of each successive frame interval. If the display element is to be set in the OFF state, then during each row selection interval R.sub.N of that display element, signal V.sub.SEG goes to the +V.sub.L level, so that a potential of only (V.sub.H -V.sub.L) is applied across the display element during row selection interval R.sub.N, in successive frame intervals. Ideally, an RMS voltage value of sufficient magnitude to produce maximum "dark state" density should thereby be applied to each display element which is addressed to be set in the ON state, while an RMS voltage producing a perfect "light state" density should be applied to each display element which is addressed to be set in the OFF state.

An identical effect can be obtained if the polarities shown in FIGS. 2A and 2B are inverted, i.e. such that a display element is driven to the ON state by a high negative voltage, e.g. -(V.sub.H +V.sub.L) during the corresponding row selection interval, and is set to the OFF state by a low negative voltage, e.g. -(V.sub.H -V.sub.L). In the following, the condition shown in FIGS. 2A and 2B will be referred to as the positive drive state, while the opposite condition will be referred to as the negative drive state. In a practical display system, a single control signal referred to in the following as a polarity control signal is used to selectively establish these drive states. It will be assumed that when this polarity control signal is at a predetermined high potential, the positive drive state is established, while when the polarity control signal is at a predetermined low potential, the negative drive state is established.

FIG. 2C illustrates the drive voltage applied during three successive row selection intervals to a display element which is addressed during row selection interval R.sub.N, for the case in which this display element is set to the ON state while the adjacent display element (of the same column) addressed during the preceding row selection interval R.sub.N-1, is set to the OFF state and the adjacent display element (of the same column) addressed during the succeeding row selection interval, R.sub.N+1, is set to the ON state. This is the drive voltage which would be applied to display element 16b in FIG. 1, for example, during the first, second and third row selection intervals of each frame interval, if that display element is set in the ON state and display elements 16a and 16c are set in the OFF and ON states respectively. FIG. 2D shows the corresponding drive voltage waveform for this display element for the case in which it is set to the OFF state, while the preceding and succeeding display elements remain in the OFF and ON states respectively.

For each display element, the portion of each frame interval during which the display element is not addressed will be referred to as the non-selection interval. Thus, row selection intervals R.sub.N-1 and R.sub.N.sub.+1 fall within the non-selection interval of a display element which is addressed during row selection interval R.sub.N. It can thus be understood that for the positive drive state, the drive voltage applied to a display element during any specific row selection interval within the non-selection interval of that display element will be positive (e.g. +V.sub.L) if the display element which is in the same column of the element array as the first-mentioned display element and is addressed during that row selection interval is driven to the ON state, and will be negative (e.g. -V.sub.L) if the latter display element is driven to the OFF state. When the negative drive state is established, the opposite will be true. That is, the drive voltage applied to a display element during any specific row selection interval within the non-selection interval of that display element will be negative (e.g. -V.sub.L) if the display element which is in the same column of the element array as the first-mentioned display element and is addressed during that row selection interval is driven to the ON state, and will be positive (e.g. +V.sub.L) if the latter display element is driven to the OFF state.

Due to the resistance-capacitance impedance effect described hereinabove, the actual drive voltage waveform applied to a display element will not be of square shape, but will be distorted as indicated by dotted-line portion 18 in FIG. 2C.

It is necessary to periodically alternate the polarity of the drive voltage applied to each liquid crystal display element, i.e. no DC voltage component can be applied. One drive method known in the prior art, which meets the latter requirement, is shown in the timing chart of FIG. 3. With this method, the drive voltage applied to each display element is inverted midway through each row selection interval, that is, the positive drive state (as defined above) is established during the first half of each row selection interval, and the negative drive state during the second half. FIG. 3 shows the drive voltage applied during one frame interval to a display element which is addressed during row selection interval R.sub.1, i.e. the selection interval t.sub.1 for this display element corresponds to row selection interval R.sub.1, while the non-selection interval (t.sub.2) corresponds to the remaining row selection intervals of each frame interval. In the example of FIG. 3, all of the display elements of the column containing the addressed display element are set in the ON state. It will be apparent that if all of the other display elements in that column are set in the OFF state, then the drive voltage applied to the latter display element will be identical to that shown in FIG. 3, during the non-selection interval t.sub.2, but will be shifted in phase by 1/2 of a row selection interval, i.e. by 1/2H.

With this drive method, no DC component is applied to a display element, and in addition, the number of transitions of potential of the drive voltage applied to a display element which occur in each frame interval will be independent of the display pattern formed by the other display elements of the column containing the latter display element. Thus, no pattern-dependent contrast variations will be produced, since the drive signal applied to each display element will contain substantially the same high-frequency components. However, due to the fact that a drive voltage polarity transition occurs in every row selection interval, the resistance-capacitance blocking effect which occurs with a large-area high element-density liquid crystal matrix display panel as described above will limit the amplitude of voltage applied to a display element which is to be set in the ON state, as illustrated for row selection interval R.sub.1 in FIG. 3, i.e. the drive voltage will vary exponentially during each half of a row selection interval. This effect cannot be overcome by increasing the common or segment drive signal voltage levels, since this will produce an increase in the effective RMS voltage value applied during each non-selection interval. In addition, the high frequency components of the drive signals required with this method result in extremely high power consumption by the drive circuits of the display panel. For these reasons, it is not possible to apply this drive method to a large-area liquid crystal matrix display panel having a high display element density. The latter method will be referred to as the A-type drive method.

Another method of driving a liquid crystal matrix display panel known in the prior art will now be described, referring to FIG. 4A and 4B. With this method, which will be referred to as the B-type drive method, a drive voltage waveform V.sub.LC is employed whereby the polarity of the drive voltage applied to each display element alternates on successive frame intervals, i.e. the positive drive state and negative drive state (as defined hereinabove) are established alternately in successive frame intervals. As a result, no inversion of the polarity of drive voltage V.sub.LC applied to each display element during a row selection interval is performed, so that this method would appear to be more suitable than that of FIG. 3 for driving a large liquid crystal matrix display panel with high element-density. FIG. 4A shows the drive voltage waveforms V.sub.COM and V.sub.SEG, and the resultant drive voltage V.sub.LC applied to the display element, for the case of a display element which is addressed during row selection interval and is set in the ON state, while the other display elements of the same column form a successive OFF-ON-OFF . . . pattern. The V.sub.LC waveform during the non-selection interval t.sub.2 of this display element will therefore be of successively alternating form, as shown, i.e. being inverted on successive row selection intervals, and so contains a large high-frequency component. This drive signal waveform will also be applied to every display element in the same column as the latter display element, during each respective non-selection interval. In the case of a liquid crystal matrix display panel having a large number of display elements and high element density, then due to the drive conductor resistance display element capacitance effect described above, this high-frequency component of the V.sub.SEG waveform will be blocked, such as to provide only a relatively small contribution to the effective value of drive voltage applied to each display element of that column. FIG. 4B shows corresponding waveforms for this drive method, for the case of a display element addressed in row selection interval R1, which is set in the ON state, but with all of the other display elements in the same column of the array being also set in the ON state. In this case, the polarity of the drive signal V.sub.LC will be inverted only at the end of each frame interval, so that the drive voltage waveform during the non-selection interval t.sub.2 contains a large low-frequency component, and this will be true for each of the other display elements within the same array column. This low-frequency component will be relatively unaffected by the resistance-capacitance blocking effect occurring in a large-area display as described hereinabove, and so will contribute a substantial amount to the effective drive voltage applied to a display element which is set in the ON state. However for the case of FIG. 4A, as described above, the drive voltage waveform contains a large high-frequency component, which is blocked from affecting the RMS value of V.sub.LC. As a result, each display element in a column of display elements which are all set in the ON state (i.e. dark-level state) will attain a greater degree of dark-state density than each ON-state display element of a column of display elements which form an ON-OFF-ON-OFF . . . alternating pattern. As a result, unevenness of display quality will result. This pattern-dependence effect is a serious problem, which will of course be worsened as the number of display elements and display element density are increased, with corresponding increases in drive conductor resistance values.

It must be emphasised that the polarity of drive voltage applied to a display element during any row selection interval within the non-selection interval of that element within a frame interval will be determined by the combination of the display state (ON or OFF) to which the other element within the corresponding column, addressed during the latter row selection interval, is driven, and the drive state (positive or negative) established by the polarity control signal as described hereinabove. This relationship is illustrated in Table 1 below, in which +.sub.D denotes the positive drive state and -.sub.D the negative drive state, "1" denotes the ON state of a display element, and "0" the OFF state,

TABLE 1 ______________________________________ Drive state during .sup.+ D .sup.- D row selection interval R.sub.n State of display element 1 0 1 0 addressed during R.sub.n Polarity of drive voltage + - - + applied during R.sub.n to any other (i.e. non-addressed) element in same column. ______________________________________

This display pattern dependency problem which arises with the B-waveform drive method is illustrated in FIGS. 5A and 5B. Here, the capital letter F is displayed vertically, with the vertical bar portion of the letter being formed by a set of 7 display elements which are driven by a segment conductor denoted as SEG1. Thus, these 7 display elements are held in the ON state. The remaining portions of the letter are formed by alternating ON and OFF states of three other columns of display elements, driven respectively by segment conductors designated as SEG2, SEG3 and SEG4. As illustrated in FIG. 5B, Using the B-waveform drive method described above with a large display having high element density, the vertical bar portion 24 of the letter will appear darker than the horizontal portions 26, 28. In addition, since a relatively large drive voltage component will be applied to each display element of the column containing vertical bar 24 which are set in the OFF state, due to a low-frequency component of the drive signal applied to each of these display elements being produced as described hereinabove, these display elements will not be set completely in the OFF (i.e. light) state, but will be driven to some extent into the ON state, so that they will appear darker than adjacent OFF state display elements on each side of that column, as indicated by numeral 20. Thus, a grey vertical band will appear in the column containing vertical bar portion 24. If a number of such vertical bar portions occur within the same array column, then this vertical band will become of correspondingly darker appearance than the display background color. A corresponding effect occurring in vertically aligned region 22, corresponding to horizontal bar portions 26, 28, will be much less apparent, due to the blocking effect of drive signal high frequency components described above.

The basic concepts of the method of the present invention will now be described. Firstly, referring again to FIG. 4A, and examining the non-selection interval t.sub.2 of a display element which is addressed during row selection interval R.sub.1, there are four possible modes of drive voltage polarity transition (referred to in the following as polarity alternation sub-sequences) which can occur during any successive pair of row selection intervals within this interval t.sub.2. These are, for example in the case of row selection intervals R2 and R3 in FIG. 4A, a sequence of negative polarity during R2 and positive polarity during R3 (as in FIG. 4A), a sequence of two intervals of positive polarity, during R2 and R3, (i.e. as in FIG. 4B), a sequence of positive polarity during R2 and negative polarity during R3, and a sequence of two intervals of negative polarity, i.e. during both R2 and R3. It is a fundamental feature of the present invention that, for any such pair of consecutive row selection intervals during the non-selection intervals of any display element, all of the above sequences of drive voltage polarity alternation will occur during each of consecutively occurring sets of four consecutive frame intervals. As a result, the total number of drive voltage polarity alternations which occur during the non-selection intervals of a display element, as measured over such a set of four consecutive frame intervals, will be constant, irrespective of the display pattern formed by the other display elements of that array column.

The manner in which is is accomplished will now be described, referring first to FIG. 6. With the present invention, the drive voltage applied to any mutually adjacent pair of display elements in an array column, during the two successive row selection intervals in which these display elements are respectively addressed in each frame interval, is controlled in accordance with four different subsequences respectively in every four successive frame intervals. These drive voltage control sub-sequences are designated as as.sub.0 to ss.sub.3 in FIG. 6. With ss.sub.0, the positive drive state (ss defined hereinabove) indicated as +.sub.D, is applied during both of the abovementioned two successive row selection intervals (designated as R.sub.N and R.sub.N+1). With ss.sub.1, the negative drive state (as defined hereinabove and indicated as -.sub.D) is applied during both R.sub.N and R.sub.N+1. With ss.sub.2, the positive drive state is applied during R.sub.N and the negative drive state during R.sub.N+1. With ss.sub.3, the negative drive state is applied during R.sub.N and the positive drive state during R.sub.N+1. Each of these four sub-sequences is implemented times in each of successive groups of frame intervals, which will be referred to as cycle intervals, with each cycle interval consisting of 4 successive frame intervals, where is an integer. The four sub-sequences occur in a fixed order within each cycle interval, which can be arbitrarily determined. The length of each cycle interval is preferably made equal to 4 frame intervals, and this value will be assumed in the following unless otherwise stated.

The effect obtained by this procedure are illustrated in FIG. 7. This is a table which shows the voltages (e.g. +V.sub.L or -V.sub.L in the example of FIGS. 2C, 2D) which are applied during row selection intervals R.sub.N and R.sub.N+1, for four successive frame intervals F.sub.a to F.sub.a+3, to any display element which is not addressed during either of the latter intervals. The table shows how these non-selection applied voltages vary in accordance with the display pattern produced by the two display elements which are in the same column as the latter display element and which are addressed during intervals R.sub.N, R.sub.N+1 respectively in each frame interval. For example, if display elements 16b, 16c in FIG. 1 are addressed during R.sub.N, R.sub.N+1, then the column "Display pattern" in FIG. 7 indicates the display patterns which can be produced by these two elements, and the table shows the resultant voltages which will be applied to a non-addressed element (e.g. element 16a) during four successive frame intervals. It is assumed that the drive voltage polarity alternation sub-sequences are applied to these two display elements in the order ss.sub.0, ss.sub.1, ss.sub.2 and ss.sub.3 in the four successive frame intervals of each cycle interval. In FIG. 7, the application of a positive polarity drive voltage during a non-selection interval is indicated by the + symbol (e.g. corresponding to application of voltage +V.sub.L in the example of FIG. 2C above) and the application of a negative polarity drive voltage during the non-selection interval is indicated by the "-" symbol (e.g. corresponding to voltage -V.sub.L in the example of FIG. 2C). The ON state of a display element is indicated as 1, and the OFF state as 0. The case in which the display pattern produced by the two adjacent display elements addressed during intervals R.sub.N, R.sub.N+1 is 00 (i.e. both display elements are set to the OFF state) will be described first. During the first frame interval of a cycle interval, (indicated as frame 4N), when ss.sub.0 is established, negative polarity drive voltage (e.g. -V.sub.L) will be applied to each non-addressed display element within the column concerned, during both of row selection intervals R.sub.N and R.sub.N+1. During the next frame interval, (when sub-sequence ss.sub.1 is established) the positive polarity drive voltage (e.g. +V.sub.L) will be applied to each non-addressed display element in that column, during both R.sub.N and R.sub.N+1. During the third frame interval of the cycle interval (in which subsequence ss.sub.2 is established) the negative drive voltage will be applied during R.sub.N and the positive drive voltage during R.sub.N+1. During the fourth frame interval of the cycle interval (in which sub-sequence ss.sub.3 is established), the negative drive voltage will be applied during R.sub.N and the positive drive voltage during R.sub.N+1. It can thus be seen that for a display pattern consisting of two OFF state display elements disposed mutually adjacent in a matrix column, a total of four alternations of drive voltage polarity will occur during the non-selection intervals of every other display element in the column containing the latter two display elements, as measured over four consecutive frame intervals.

It will be apparent that the same will be true for each of the other three possible display states produced by these two display elements, indicated as 01, 10 and 11 in FIG. 7. Thus, since any display pattern formed by a column of display elements must consist of combinations of the four patterns 00, 01, 10 and 11, the number of polarity alternations of drive voltage which take place during the non-selection intervals of any display element, as measured over any four successive frame intervals with this embodiment, will be independent of the display pattern formed by that column.

Three possible methods of drive voltage control to implement the above drive voltage sub-sequences are illustrated in FIGS. 8A, 8B and 8C, in which waveforms of the polarity control signal referred to above are shown, with it being assumed as stated above that the positive drive state is produced when the polarity control signal is at a high potential, and the negative drive state when the polarity control signal is at a low potential. Firstly, with the method shown in FIG. 8A, four waveforms of the polarity control signal having an identical period, which mutually differ in phase and are designated as .phi.0 to .phi.3, are applied respectively during the four successive frame intervals of each cycle interval. For comparison of the phase relationships of these four waveforms, each is shown as beginning at a fixed timing T.sub.0 which is arbitrarily determined with respect to the start of a frame interval. Each waveform comprises a periodic repetition of two row selection intervals in which the positive drive state (high potential of the polarity control signal) is established followed by two row selection intervals in which the negative drive state (i.e. low potential of the polarity control signal) is established