An image memory controller having a first address signal generating unit generating a first address signal in response to a state signal representing the operational state of a printer. The first address signal corresponds to a location in an image memory. A second address signal generating unit generates a second address signal for refreshing the image memory and a third address signal generating unit generates a third address signal used for rewriting at least part of data stored in the image memory. An address signal selector selectively delivers any of the first, second, and third address signals to the image memory.

A printer has test circuitry external to its processor to test memories used inside the printer. The test is initiated by the processor by signalling the test circuitry. The test circuitry stores a first sequence in each memory then reads the sequence from the memory and compares the memory's data to the original sequence. The test is repeated with a second sequence which is the logical inverse of the first sequence. If an error occurs, a flag is set. When the test is complete, the processor is notified. The processor can check the error flag to determine whether the test was successful.

A new printer having a memory for storing dot image data to be printed, wherein two modes, that is, a full bit map mode for storing a page of data and a strip map mode for a smaller size of data than a page of data is stored alternately in two memory areas in the memory are provided, and the full bit map mode or the strip map mode is selected according as the size of image data is smaller than or not. In the full bit map mode, the bit data are sent to the printing means after all the bit data of a page has been stored in the bit map memory, while in the strip may mode an image of one page is divided into a plurality of image portions and the bit data is written/read to and from the bit map memory in the unit of image portion. In a new printing method, the size of an image of one page to be printed is obtained first. Then, if the obtained size of image is smaller than the capacity of a bit map memory for storing bit data, the full bit map mode is set; otherwise the strip map mode is set. Next, bit data received from the bit map memory is printed on a sheet of paper.

A data register is provided through a column gate circuit in a ROM array in which font information is stored. Desired font information is read out as parallel data through the column gate circuit based on address information inputted to a row decoder and a column decoder. The data read out is stored once in the data register. Thereafter, the parallel data stored in the data register is outputted to a printing output circuit as serial data in synchronization with reception by a printing output circuit, thereby to perform printing processing. Consequently, font information to be printed need not be stored in a RAM or the like through a data bus, so that processing is simplified and the speed of a processing operation is increased.

Clocking circuitry for a character generator wherein a control microprocessor controls character generated by hardwired logic through an interface microprocessor, the clocking circuitry including an oscillator which supplies an output to a divider which supplies a reduced frequency signal to the control microprocessor. The output of the oscillator is also supplied to the output of a timing controller. The timing controller further receives a print signal from the interface microprocessor and supplies a plurality of timing signals to the hard wired logic character generator.