A method of linking peripheral devices to a single interrupt procedure in a computer is comprised of storing in an interrupt vector table of a BIOS ROM, a first pointer to an interrupt service routine related to one of a group of peripheral devices which use the same interrupt request (IRQ) on the same software interrupt vector, and storing further pointer in each one of the peripheral devices to another unique one of the peripheral devices in the group.

A microprocessor for performing an interrupt operation receives an interrupt-enable signal representative of occurrence of at least interrupt request and interrupt level information representative of a selected one of interrupt sources issuing the interrupt request and includes an interrupt receiving unit activated by the interrupt-enable signal for producing vector fetching command information when an interrupt operation responsive to the interrupt level information is acceptable, an interrupt vector generation unit activated by the interrupt-enable signal for generating interrupt vector information, and an execution unit fetching the interrupt vector information in response to the vector fetching command information, the execution unit thereby initiates an interrupt operation by use of the interrupt vector information and returning interrupt acknowledge information as a part of the interrupt operation.

A system includes first and second processing units which are interconnected by a bidirectional bus. The first processing unit is a microprocessor chip programmed for executing procedures stored in an on-chip instruction cache unit. The second processing unit receives requests from an external source such as a system bus. The microprocessor chip includes a branch vector facility which connects to the bus. The second processing unit in response to an external request, generates a vector branch address. The processing unit transfers the vector branch address to the branch vector facility for storage along with setting a write indicator. The microprocessor chip, upon detecting that the write indicator was set, branches to the procedure specified by the branch vector address for executing the instructions of the procedure to carry out those operations required for processing the external request or event.

In an interruption circuit, each of a multiplicity of interruption generating units (12) is for generating an interruption signal upon occurrence of an interruption request. A scanning arrangement scans the units to specify one of them at a time as a particular unit and to supply the signal generated by the particular unit to a CPU (11) as a particular signal. A response supply arrangement supplies the particular unit with a response produced by the CPU upon receipt of the particular signal. Supplied with the response, the particular unit supplies the CPU with an interruption vector which is specific to each unit and makes the CPU interrupt its operation related to the particular unit. Preferably the scanning arrangement comprises a scanning circuit (16) and a first plurality of polling circuits (17), each for a second plurality of generating units with a response control circuit (27) made to correspond thereto.

A data transfer system including a byte bus which provides an eight-bit data transfer between a processor and a plurality of port circuit boards. The system provides dual address and interrupt functionalies in the processor-initiator data transfers which may be initiated in either direction. The processor data transfers use a two-level address management scheme, which once initialized provides rapid access to a select number of address locations from a large number of available addresses allocated to a variety of port circuit boards and addressable functions thereon. Furthermore, the select addresses are assignable according to an interrupt priority value which allows for the rapid identification of the address requesting an interrupt service, and also for the subsequent provision of an interrupt service vector to the processor to provide the appropriate processing of the requested interrupt. The resulting apparatus and method provides substantial compaction of the communication data distribution system and software driving utilities.