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REFERENCE TO RELATED APPLICATIONS
CONTENTS
BACKGROUND OF THE INVENTION
A. Field of the Invention
B. Description of the Prior Art
SUMMARY OF THE INVENTION
BRIEF DESCRIPTION OF THE DRAWINGS
DESCRIPTION OF THE PREFERRED EMBODIMENT
A. The Present Invention Resides in a High Performance Storage Unit (HPSU)
B. The Problem Solved by the Present Invention
C. General Description of the HPSU
D. Detailed Description of the HPSU Block Diagram
E. Timing of the HPSU Within Which the Circuit Apparatus of the Present
Invention Resides
F. The Circuit Apparatus of the Present Invention
G. Timing Diagram of the Operation of the Present Invention
CLAIMS
ABSTRACT
REFERENCE TO RELATED APPLICATIONS
The instant application claims subject matter related to, and a circuit
apparatus contained within a memory apparatus taught within, another
patent application filed on Apr. 2, 1984, the other application being
further identified as: U.S. Ser. No. 596,130 entitled "High Performance
Storage Unit", filed in the name of J. H. Scheuneman.
The instant application also claims subject matter disclosed in a related
application filed on the same day as the instant application, such other
related application being further identified as:
U.S. Ser. No. 630,140 entitled "Forced Clear of a Memory Time-Out to a
Maintenance Exerciser" filed in the names of D. K. Zenk, et al., now U.S.
Pat. No. 4,590,586.
All three applications are assigned to common assignee Sperry Corporation,
a corporation of the State of Delaware having a place of business at 1290
Avenue of the Americas, New York, New York 10019.
The instant application is related to the following co-pending patent
applications:
Title: MULTIPLE OUTPUT PORT MEMORY STORAGE MODULE
Inventor: James H. Scheuneman and Gary D. Burns
Ser. No.: 596,214
Filed: Apr. 2, 1984
Title: READ ERROR THROUGH-CHECKING SYSTEM
Inventor: James H. Scheuneman Ser. No.: 354,340
Filed: Mar. 2, 1982, now abandoned
Title: READ ERROR OCCURRENCE DETECTOR FOR ERROR CHECKING AND CORRECTING
SYSTEMS
Inventors: Gary D. Burns and Scott D. Schaber Ser. No. 464,184, now U.S.
Pat. No. 4,523,314
Filed Feb. 1, 1983
Title: MULTIPLE UNIT ADAPTER
Inventor: James H. Scheuneman
Ser. No.: 596,205
Filed: Apr. 2, 1984
Title: A PRIORITY REQUESTER ACCELERATOR
Inventors: John R. Trost and Daniel Zenk
Ser. No.: 530,285
Filed: Aug. 31, 1983
Title: PARTIAL DUPLEX OF PIPELINED STACK WITH DATA INTEGRITY CHECKING
Inventor: James H. Scheuneman, et al.
Ser. No.: 595,864
Filed: Apr. 2, 1984
Title: PIPELINED DATA STACK WITH ACCESS THROUGH-CHECKING
Inventor: James H. Scheuneman
Ser. No.: 596,131
Filed: Apr. 2, 1984
Title: MULTIPLE PORT MEMORY WITH PORT DECODE ERROR DETECTOR
Inventor: James H. Scheuneman
Ser. No.: 596,132
Filed: Apr. 2, 1984
Title: HIGH PERFORMANCE PIPELINED STACK WITH OVER-WRITE PROTECTION
Inventor: Wayne A. Michaelson
Ser. No.: 596,203
Filed: Apr. 2, 1984
Title: AN IMPROVED ACCESS LOCK APPARATUS FOR USE WITH A HIGH PERFORMANCE
STORAGE UNIT OF A DIGITAL DATA PROCESSING SYSTEM
Inventors: Daniel K. Zenk and John R. Trost
Ser. No.: 596,202
Filed: Apr. 2, 1984
Title: MULTILEVEL PRIORITY SYSTEM
Inventors: James H. Scheuneman and W. A. Michaelson
Serial No.: 596,206
Filed: Apr. 2, 1984
Title: PIPELINED SPLIT STACK WITH HIGH PERFORMANCE INTERLEAVED DECODE
Inventors: James H. Scheuneman and W. A. Michaelson
Ser. No.: 596,215, now U.S. Pat. No. 4,600,986
Filed: Apr. 2, 1984
All applications are assigned to common assignee Sperry Corporation, a
corporation of the state of Delaware having a place of business at 1290
Avenue of the Americas, New York, New York 10019.
BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention generally concerns the prioritization of requestors
utilizing a digital computer memory servicing a plurality of such
requestors. The present invention specifically concerns that modification
which needs to be made to the snapshot scheme of prioritizing requests to
a digital computer memory when two requestors share a single memory port.
Since such modification will be seen to allow that requests arising from
each such two requestors sharing a said prioritized single memory port
will both be honored, in sequence, during a single priority scan, then
such modification is not perceived to be of much efficacy over according
each such requestor a separate port if (1) the requestors are often in
contention and (2) separately prioritized ports are readily available. But
if (1) separately prioritized ports are minimized in numbers in order to
save time in the priority circuitry prioritizing simultaneous requests
received at such, and (2) some two requestors are not often simultaneously
contending to request a digital memory, then the modification to memory
priority, specifically snapshot priotity, of the present invention which
accords that two requestors should share but a single prioritized memory
port is efficient in allowing n+1 requestors to utilize an n-wide priority
network, and effective in minimizing the delay encountered in a priority
network since an n-wide network is generally faster than an (n+1)-wide
network. Further specifically, the present invention teaches that a memory
maintenance exerciser type requestor, being a requestor generally but
infrequently requesting a memory for the purposes of the operational
validity checking and maintenance thereof, should share a single memory
port with a normal requestor of such memory, nominally called an
Instruction Processor, or IP.
B. Description of the Prior Art
The environment of the apparatus and method of the present invention is a
very large scale, very high performance, digital computer memory unit such
as is described in U.S. patent application Ser. No. 596,130. It is a known
maintainability feature in the prior art for very large scale, very high
performance, computer memory units that the memory stores of such units
should be dynamically partitionable into those dedicated to applications
and those upon which, the memory unit remaining on-line, operational
validity checking and maintenance may be exercised. The utility of
exercising maintenance--being the exercise and validity checking of logic,
error correction/detection logic, and memory stores--upon part of the
memory stores of a very large scale memory unit while such large scale
memory unit is, in the areas of stores not being exercised for
maintenance, elsewise devoted to applications operation, is that such
maintenance may be often performed with minimum conflict to the system
utilization of that system resource, the memory unit, which may be very
expensive. The on-line maintenance exercise of parts of the stores of a
very large scale memory unit also provides the maximum potential for the
detection and isolation of intermittent fault phenomena within the logics
of such memory units as well as within those stores of such units detached
to on-line maintenance testing.
It is known in the prior art that the maintenance exerciser which
administers the regimen of read, write, and partial write on-line testing
to a portion of the stores of a high performance memory unit, which memory
unit is elsewise involved in servicing systems applications with the other
stores contained therein, may be either internal to such memory unit or
external to such memory unit. In either case, however, there is usually an
external agency to the memory which does both configure the memory for
test (i.e., designate which of the memory stores are to be devoted to
on-line memory test and which are to be devoted to systems applications)
and shepherd the progress of such testing (if not actually administering
same), obtaining the results thereof. In other words, even if a
maintenance exerciser is internal to a very large scale memory unit, the
fault detections of such maintenance exerciser needs be communicated to
the computer system, and such computer system needs (if possible)
reconfigure such high performance memory unit to operability, through an
interface to such high performance memory unit. Such an interface is
normally in the prior art a memory port fully capable of normal memory
command, read, and write operation. The device connected to such an
interface is normally called a maintenance processor, or a System Support
Processor(SSP).
It is also known in the prior art that a single memory unit may communicate
with a plurality of requestors, and may employ diverse priority schemes in
the determination of which of such requestors shall be next serviced. One
of such prior art priority schemes for the resolution of access between
requestors communicating with a single memory unit is "snapshot" priority
determination. In a "snapshot" priority scheme, the total one or ones of
requestors which are attempting communication with the memory unit at a
particular time will be frozen, or "snapped", into a queue. Such a queue
will be completely serviced in priority order before any request not
originally "snapped", or any reinstitution of "snapped" requests once
serviced, will be registered or considered. Such scheme is tantamount to
the taking of a photographic "snapshot" of pending memory requests, and
servicing all such requests in priority order prior to the taking of
another "snapshot".
An obvious accommodation between the prior art fully-functional ported
access which is taken of a memory unit for the purposes of maintenance
thereof (including through an internal maintenance exerciser operating
on-line to the normal system operation of such memory unit) and a snapshot
priority scheme at the requestor's interface to such memory unit is that
the maintenance port, and the maintenance processor or system support
processor requestor connected thereto, should be handled in such snapshot
priorities equivalently to other system requestor types. Such is generally
the scheme in the prior art, and it may be noted that the maintenance port
is, in accordance with the test function performed thereon, normally
accorded the lowest system priority in the snapshot or any other memory
priority scheme.
It is also known in the prior art to configure a snapshot priority scheme
so that requests from the exerciser and requests from a normal requestor
external to such memory will share a single port of access to such memory.
The utility of such sharing is that the breadth of the priority
determination logics may be narrowed by the fact that the exerciser and a
normal requestor do share a single port, and all internal control and data
paths of the memory by which the exerciser, whether internal or external,
does exercise such memory are, of course, identical to the paths elsewise
utilized by the normal requestor sharing the same port of access. The
process of "sharing" implies, however, its own, subsidiary, priority
determination scheme. In the prior art, this subsidiary priority
determination scheme was operationally effective, and was based on
historical record keeping. Mainly, requests arising from the exerciser and
from the normal requestor with which it shared a port were resolved, as
between themselves, before further submission to the normal, snapshot,
priority request scheme. A history was kept of each request occurring from
the exerciser and from that normal requestor sharing the same port. If
both the exerciser and the requestor sharing the same port made requests
during the same priority snap, then normally the normal requestor only
would be passed to further priority determination, wherein it would be
ultimately honored in normal snapshot priority. A history of this
occurrence was kept. Upon a next subsequent exerciser report request upon
a next subsequent priority snap, such exercise port request would be
honored regardless of whether there should be another, subsequent, request
from the normal requestor sharing the same port or not. If there was such
a next subsequent request from the normal requestor sharing the same port,
it would be held waiting until the next priority snap to be gated to
snapshot priority in preference over further requests of the exerciser,
should such be present. The sharing of a port between an exerciser and a
normal requestor thus was accomplished with first one, and then the other,
going foremost upon any simultaneous requests from both. In order to
determine which one should be foremost at any one time, history keeping of
the requests of both was required.
SUMMARY OF THE INVENTION
The present invention is a method and apparatus for the modification of
snapshot priority as performed by a memory unit for the prioritization of,
and amongst, a plurality of ported requests to read or write such memory
unit arising from a like plurality of requestors. In particular, the
present invention concerns a modification of such memory snapshot priority
as will accord that a normal requestor, making requests to read or write
such memory, may share, in a snapshot priority scheme, a single
prioritized port of such memory with a maintenance exerciser of such
memory. A maintenance exerciser, which may be either internal to or
external of, such memory, is but a circuit, or device, which reads or
writes the memory, in a conventional manner to the reading or writing of
normal memory requestors, to the end that the memory may be tested, and
the correct functionality thereof determined. That such a maintenance
exerciser, involved in the maintenance of a memory unit, should, at the
threshold, share a port of access to such memory with a normal requestor
of such memory is desirable because (1) the number of requestors
servicable within a snapshot priority space of identical width is
augmented by one, (2) the functionality of such memory exercised and
validated by the exerciser will be, at least, substantially identical to
that functionality of the memory elsewise seen by the requestor which does
share the identical port, and (3) the width of the (snapshot) priority
determination entwork will be minimized, allowing such network to operate
faster.
The present invention permits of the maintenance exerciser and the normal
requestor which do share a single port, and therefor but a single entrance
into the snapshot priority evaluation scheme of a memory unit, to both be
honored in a single priority snap. With the present invention, no history
keeping concerning the honoring of competing requests from the exerciser
and from the normal requestor sharing the same port needs be kept. Also,
because both the exerciser request and that arising from the normal
requestor sharing the same port will be honored within the same priority
snap, a quicker average response to both such exerciser and such normal
requestor is obtained than if the access of one such, either the exerciser
or the normal requestor, to memory was alternately to be delayed until the
next successive priority snap.
The circuit of the present invention functions to modify normal snapshot
priority within a memory unit to cause that, upon such times as an
exerciser and a normal requestor request are both present upon the same
port, the normal requestor will be (first) honored, and the exerciser will
be (next) honored both within the same priority snap. Such is accomplished
by postponing a new priority snapshot for such additional time as will
accord that both the requests of the exerciser and of that normal
requestor which do share a single port of access into such snapshot
priority may be honored within the same priority snap.
Consequently, it is a first object of the present invention that a memory
unit operative with snapshot priority to honor a plurality of requests
occurring on a plurality of ports of such memory unit, one of such ports
being shared by both an exerciser and a normal requestor of such memory
unit, may perform modified snapshot priority to the end that competing
requests between such exerciser and such normal requestor which does share
the same port may both be honored within that same priority snap upon
which both requests were made.
It is a second, subsidiary, object of the present invention that the
modification to snapshot priority of a memory unit which does accord that
both an exerciser and a normal requestor which do share a same port into
such memory unit may both be honored upon a same priority snap will
additionally accord that the normal requestor shall be first satisfied,
and then that the exerciser shall be next satisfied, in the satisfaction
of both within the same priority snap. When that port which the exerciser
and the normal requestor share is the lowest overall priority port within
the overall snapshot priority scheme of the memory unit, then this
sequence assures that the exerciser requests are of lowest overall
priority, meaning last serviced within one priority snap, of all such
requests occurring to the memory unit.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1, consisting of FIG. 1a and FIG. 1b, shows a block diagram of the
High Performance Storage Unit within which the present invention resides.
FIG. 2 shows a detailed block diagram of the timing of the HPSU in order
that it may interface with requestors of two disparate interface
communication cycle times.
FIG. 3, consisting of FIG. 3a through FIG. 3c shows a timing diagram of the
8-phase and of the 4-phase clocks which are utilized by different types of
requestors in communication with the HPSU, and the possible times of
occurrence of the initiation of reading the storage memory bank, and of
the gating of the results output therefrom such reading, relative to the
clock phases of each of the 4-phase and 8-phase clock timing chains.
FIG. 4, consisting of FIG. 4a and FIG. 4b, shows the circuit schematic of
the present invention modifying snapshot priority in order to enable two
requestors to share a single memory port.
FIG. 5, consisting of FIG. 5a and FIG. 5b, shows a timing diagram of the
operation of the circuit of the present invention shown in FIG. 4.
DESCRIPTION OF THE PREFERRED EMBODIMENT
A. The Present Invention Resides in a High Performance Storage Unit (HPSU)
The present invention resides in, and is utilized in the functional
performance of, a High Performance Storage Unit (HPSU) which is the
subject of U.S. patent application Ser. No. 596,310, the entire contents
of which are incorporated herein by reference. For the sake of
completeness, certain of the description of such an HPSU is herein
provided.
The HPSU resides in a digital data processing system which is essentially
modular, and provides for parallel processing. Normally, from one to four
Instruction Processors (IPO through IP3) will be interfaced to the HPSU.
Each IP can, for example, be a Type 3054-00 unit available from Sperry
Corporation, or such other Instruction Processor available commercially as
would be compatible. The IP provides basic mode and extended mode
instruction execution, virtual maching capability, and contains two buffer
memories: one an operand buffer, and the other an instruction buffer. Each
IP is functional to call instructions from memory, execute the
instructions, and in general does data manipulation. The IP also executes
instructions to set up input and output data buffers and channel access
control. It is one of such IP's --specifically IP3--which is one of the
two requestors which share a single memory port under the modified
snapshot priority apparatus and method of the present invention.
In conjunction with the IPs, from one to four Input/Output Processors (IOP0
through IOP3) are also normally interfaced to the HPSU. The
interconnections between the HPSU and the IPs and the IOPs are in fact
direct connections between each unit, and the interconnection is not
bused. Each IOP can be a Type 3067-00 unit available from Sperry
Corporation, or an equivalent type of processor. The IOPs handle all
communications between the IPs, and the memory systems, and the peripheral
subsystem. In this type of configuration, the IPs function as the system
Central Processing Units, and the IOPs act as CPUs to handle all of the
communications. The IPs and IOPs are commonly referred to as the 1100/90
system.
From one to four High Performance Storage Units (HPSU0 through HPSU3) can
be utilized in a system. Each HPSU is a free-standing unit with eight
memory banks, each bank containing 524K storage data words. Error
Correction Code (ECC) is used internal to each HPSU to provide single-bit
error correction and double-bit error detection.
Each HPSU provides four Instruction Processor (IP) ports for providing
communication paths to the IPs, both for reading and writing. Again it
should be understood that inter-connection between each HPSU and each IP
is directly cabled, and is not bused. Each HPSU also includes four
Input/Output Processor (IOP) ports for interconnection with the IOPs.
These interconnections are direct cables between each HPSU and each IOP.
The IP and the IOP ports are each two-word read and write interfaces,
where each word contains 36 data bits and is accompanied by four parity
bits. The IOP and IP interfaces operate on a 60 nanosecond interface cycle
time.
Each HPSU also includes at least one Scientific Processor (SP) port, and in
the embodiment of this disclosure has two such SP ports. Each SP port has
a four-word data interface. If a single SP is used with a single HPSU, it
may be coupled directly to the SP port of such HPSU. When two or more
HPSUs are used with an SP, it is necessary to provide a Multiple Unit
Adapter (MUA) for each SP. Regardess of whether or not interfaced through
a MUA, each SP interface reads or writes four words, where each word
contains 36 data bits and is accompanied by four parity bits, upon each
interface cycle time of 30 nanoseconds.
Each SP functions under direction of one or more of the IPs to perform
scientific type calculations in a support mode. In this regard, the IPs
can be considered to be host processors and the SPs can be considered to
be support processors, all operating through the common storage of the
HPSU(s).
The overall system maintenance and supervision is accomplished through one
or two System Support Processors which are connected to all units of the
system. The SSP is available commercially and is utilized in the Sperry
Corporation 1100/90 Systems. In general, it is understood that each SSP
performs the function of a hardware maintenance panel for the system. The
display and setting of information, the activation at most maintenance
facilities, selecting modes of operating and the like, is done at the
control section of the SSP. The primary maintenance facility of the HPSU
which is activated in order to obtain a test of the HPSU operational
validity in reading, writing, and storing data is called the maintenance
exerciser. Such maintenance exerciser is an internal logical capability of
the HPSU, which capability may be implemented by a microprocessor
executing firmware, to exercise the memory function. In the preferred
embodiment of the invention it is this maintenance exerciser, which does
make requests to read and write the memory stores equivalently as if it
were a normal requestor and most specifically an IP type requestor, which
does, with IP3, share a single memory port under modified snapshot
priority within the preferred embodiment of the invention. The existence
of an HPSU-internal maintenance exerciser needs not be specified for the
utilization of the present invention. Indeed, an external SSP, which is an
entire computer and which may be specified to be an IP-type or
IP-equivalent computer, may directly perform the detailed test and
exercise regimen which is suggested, in the preferred embodiment of the
invention, to be better performed by specialized test logic within the
HPSU. Indeed, the present invention will serve to allow any two like-type
requestors normally communicative with two like-type memory ports to
instead share, in the snapshot priority, but a single port. That two
requestors should "share" a single port means that either requestor making
a request upon such port will be serviced at the priority of such port,
and if both requestors do simultaneously make requests upon the single
port then, at the priority of such port amongst all ports, first one
requestor and then the second requestor will each be sequentially
serviced. Such functionality may sound but semantically different than
that each such two "port sharing" requestors should each be individually
prioritized until it is realized, amongst other things, that the priority
network will remain "n" ports wide, and operate at speeds commensurate
with the prioritization of "n" ports, while the number of requestors
serviced by such priority network will be of number "n +1". In the
preferred embodiment of the present invention n=4. Consider also that an
(n=4)-wide snapshot priority network exists to prioritize amongst 4 IOP's.
When the enhancement circuit of the present invention is utilized, then an
identical snapshot priority network may be utilized to prioritize amongst
a full 4 IP's plus another requestor, called a maintenance exerciser.
Continuing in the description of the HPSU within which the present
invention resides, a clock system is utilized to maintain synchronous
operation of the entire system. Clock and synchronizing signals are sent
to each IP as well as each HPSU, each IOP, and each SP. The clock
interface includes signals and commands from the IP for controlling clock
rates, clock mode, cycle count, and other capabilities of the clock.
Intercommunication between units is essentially on a Request and
Acknowledge basis, and the interfaces will be described in more detail as
appropriate.
B. The Problem Solved by the Present Invention
In the prior art the IP3 and maintenahce exerciser requests to their shared
port were processed such that each would not be honored in the same
priority snap upon which both requests were registered. In the request
scheme, history was kept of each IP3 and maintenance exerciser request. If
IP3 and maintenance exerciser both made requests upon same priority snap,
then only the IP3 request would be honored. The maintenance exerciser
request would then be honored in the next priority snap, regardless if
there is an IP3 request or not. If there was an IP3 request, it had to
wait until the next priority snap before getting honored. Consequently,
history keeping was necessary for IP3 and maintenance exerciser requests
in a priority request scheme.
With the use of the present invention, history keeping is unnecessary in
honoring simultaneous IP3 and maintenance exerciser requests upon their
jointly shared port. In the priority scheme of the present invention, IP3
and maintenance exerciser requests will both be honored in the same
priority snap upon which both requests were registered. The IP3 request
will be honored before the maintenance exerciser request. After honoring
the maintenance exerciser request, which is of the lowest priority upon
that port (the IP3-maintenance exerciser shared port) which is the lowest
priority port amongst all (4) IP ports, then a new priority snap will
transpire, again prioritizing requests upon all ports.
C. General Description of the HPSU
Before commencing with the detailed description of the present invention
within sections F. and G., it is desirable to understand the HPSU within
which the present invention resides which is generally described in the
present section C. and particularly described in the following section D.,
and the timing of which is described in fillowing section E. If the
routineer in the digital computer memory art who is familiar with the
prioritization, and snapshot prioritization, of competing ported requests
to read and write a jointly shared memory store does not wish to
assimilate all the information in sections C., D., and E. in understanding
the present invention, then the following absolute minimum teaching should
be noted. First, the snapshot priority to which the circuit apparatus of
the present invention constitutes an improvement is shown as IP PRIORITY
68 in FIF. 1b. The maintenance exerciser (not shown in FIG. 1) shares a
single prioritized memory port with IP3, requests from which IP3 are
received as signal IP3 REQ on cable 203a shown in FIG. 1b. Second, the
second level priority network within the HPSU, called BANK 0 PRIORITY 60a
through BANK 7 PRIORITY 60h (shown in Fig. 1b) does acknowledge the first
level priority, e.g., IP PRIORITY 68, that a first-level-prioritized
request is accepted and is being honored and is being acted upon by signal
C' shown in FIG. 2, which signal may be observed to be distributed from
PRI (BANK) 60 to IOP, IP DATA MUX IOP, IP PRIORITY 52 56, 68, 72 which
includes IP PRIORITY 68. For the purposes of basic understanding of the
teaching of the present invention, it needs be known that the snapshot
priority network, to which the circuit of the present invention is an
improvement, does receive requests such as those from IP3 and/or from the
maintenance exerciser, and is (internally to the HPSU) acknowledged of the
successive prioritization of such requests by a deeper level within the
HPSU, this deeper level acting via signal C'. In other words, the
improvement circuit of the present invention is activated by the receipt
of (2) requests, it does act to successively prioritize such requests (the
IP3 request before the maintenance exerciser request), and is released
from completing each such successive request prioritization by, and only
by, an internal acknowledgement signal from a deeper logic level, which
internal acknowledgement signal essentially says "your (prioritized)
request is received, accepted, and is being acted upon". Third and
finally, the circuit of the present invention is timed by an 8 phase clock
appearing as 8.phi. CLOCK at the top of the timing diagram in FIG. 3. The
occurence of an IP3 and/or maintenance exerciser request(s) shown as
signal I in such FIG. 3, and the acknowledgement via signal C' (also shown
in FIG. 3) to successive prioritized requests, do provide the timing
framework within which the circuit of the present invention does operate.
Signals I and C' will later be seen in FIG. 4.
Continuing now with the complete and entire general description of the HPSU
within which the present invention resides, a block diagram of such HPSU
is shown in Fig. 1, consisting of FIG. 1a and FIG. 1b. The HPSU is a
storage device that is commonly accessible by the IPs, the IOPs, and the
SPs via the MUAs. The various devices that can be coupled to the HPSU can
have differing bit-widths of interface data transfer, and differing
interface cycle times.
In the preferred embodiment, the HPSU utilizes eight Banks of storage
devices, identified as STORAGE MEMORY BANK 0 40a through STORAGE MEMORY
BANK 7 40h of which Banks 0 and 7 are illustrated. Though not specifically
illustrated in FIG. 1, each storage memory Bank is comprised of four
Memory Modules and each Bank has a total capacity of 524K data words. Such
a word in memory is 36 data bits, and is accompanied by 8 bits which are
utilized for Error Correction Code (ECC) check bits, and for parity bits.
Each storage memory bank is arranged for receiving four words (W1, W2, W3,
and W4), and for reading out four words upon each read/write cycle time.
The STORAGE MEMORY BANKS 40a through 40h include the addressing circuitry,
the storage cells, the timing circuits, and the driver circuits, and can
be constructed from commercially available components, it being understood
that the accessing rate (read/write cycle time) must accomodate the
interface rates (interface cycle times) with the attached units.
The wide lines indicate directions of data flow, and the single lines
indicate control flow.
At the input, the HPSU has an IOP interface 202 which can accommodate up to
four IOP units at the four IOP ports labelled IOP0 through IOP3. It also
has an IP interface 203 which can accommodate up to four IPs at the four
IP ports designated IP0 through IP3. The IOP ports 202 and the IP ports
203 each operate to receive two data words (if a write is directed) plus
address, function, and start/end data using an interface clock cycle time
of 60 nanoseconds.
The HPSU also has two input SP interfaces 200 and 201 which can accommodate
two SPs at the two ports labelled SP0 and SPl. The SP input ports each
function to receive four data words (if a write is directed) plus address
and function data upon each interface cycle time of 30 nanoseconds.
The request and control signals from the IOP ports 202 are passed to the
IOP PRIORITY 52, which functions to select the particular IOP to be given
priority of access to the memory system. The selection is passed on line
54 to the IOP DATA MUX 56 which functions to select the appropriate data
and address information to pass on line 58 to the BANK MULTIPLEXER 60. The
control signals provided on control path 62 drive the REQ DECODER 64 for
selecting one-of-eight control lines 66 for providing control signals for
making storage memory bank selection.
In a similar manner, the IP ports 203a provide request signals to the IP
PRIORITY 68, which provides control signals on control line 70 to the IP
DATA MUX/STACK 72 for selecting the data and address signals that will be
provided on path 74. Similarly, the control signals on lines 76 to the REQ
DECODER 78 results in signals being provided to select one of eight lines
80 for controlling storage memory bank selection.
The two SP ports 200 and 201 are each arranged to store requests in REQ.
STACK & CTRL 82, and in REQ. STACK & CTRL 84. Additionally to SP requests,
SP data and address and function are temporarily held in SP0 DATA STACK 82
or SP1 DATA STACK 84 awaiting availability of the memory system. In
essence, the SP0 stacks and the SP1 stacks are each a first-in-first-out
(FIFO) circulating buffer. The request information feeds out of REQ. STACK
& CTRL 82 on line 86 to the REQ. DECODER & SELECTOR 206 which provides a
one-of-eight selection while data and address and function pass on line
204 to DATA SELECTOR 208 and then to BANK MULTIPLEXER 60. Similarly,
request information passes on line 94 from REQ. STACK & CTRL 84 to REQ.
DECODER & SELECTOR 207 for making selections on lines 98, while the data
and address and function passes on line 205 to DATA SELECTOR 209 and then
to BANK MULTIPLEXER 60.
The BANK 0 PRIORITY 60a through BANK 7 PRIORITY 60h each function to select
between the IOP, IP, and the two SP requests presented to each for
accessing memory. Each also functions to control the associated storage
memory bank, STORAGE MEMORY BANK 0 40a through STORAGE MEMORY BANK 7 40h,
to cycle and also to emplace data read upon one of the four storage memory
output ports SP0, SP1, IOP, and IP of such storage memory banks, which
storage memory output ports are respectively connected to SP0 wired-OR
communication buses 213, to an SP1 bus (not fully shown) like buses 213,
to an IOP bus (not fully shown) like buses 214, and to IP wired-OR
communication buses 214.
The HPSU has an IOP output AND-OR/REG. 102c capable of handling the IOP
memory resource port connection to four IOPs: IOP0 through IOP3. It also
has an IP output AND-OR-STACK/REG. 102d capable of handling IP the memory
resource port connection to four IPs labelled IP0 through IP3. Finally, it
has SP output OR/REG. 102a and OR/REG. capable of handling the respective
two SP memory resource output ports labelled SP0 and SPl. Data rates and
timing at the output ports 224, 225, 226, and 227 are commensurate to
those for the corresponding memory resource input ports previously
described.
Each HPSU is assigned an address range of 4M 36-bit words. Each STORAGE
MEMORY BANK 40a through 40h contains 512K words, and there are eight such
banks within an HPSU. A bank is four words wide. Each bank operates
independently of the other bank(s). Each receives request and output
multiplexing control through the associated bank priority via a respective
one of cables 210a through 210h, while receiving function plus start/end
control (utilized in partial word operations) from the BANK MULTIPLEXER
60i via the respective one of cables 2212a through 212h. Each receives
data and address information from the BANK MULTIPLEXER 60i also via the
respective one of cables 212a through 212h.
There are four storage memory output ports for each storage memory bank,
consisting of one IOP, one IP, and two SPs (SP0 and SP1) output ports. All
data read to any of the IOPs (0-3) is transmitted through the storage
memory IOP port, and all data read to any of the IPs is transmitted
through the single storage memory IP port at each storage memory bank.
That wired-OR communication bus 214, for example, does carry the data read
to the IP memory resource output port and thence to any of the four IPs
(IPO through IP3) requires that the output register/drivers of such memory
resource port, AND-OR-STACK/REG. 102d, should be able to logically
multiplex the read data received on bus 214 to an appropriate one IP. The
AND-OR-STACK/REG. is controlled to do so by address signals (path not
shown) received from the IP DATA MUX/STACK 72 and by priority port code
signals (path not shown) received from IP PRIORITY 68. Likewise, the IOP
memory resource port output register/drivers is controlled to logically
multiplex data received upon a wired-OR communication bus to an
appropriate destination IOP0 through IOP3 by signals received from IOP
DATA MUX 56 and IOP PRIORITY 52 (paths not shown).
The HPSU provides a Dayclock, auto recovery timer, System Status register,
maintenance exerciser, and an MCI interface. Odd parity is
checked/generated across all interfaces for the IP's, IOP's, and SP's.
The function of the HPSU, including in the performance of the present
invention, is discussed in greater detail in the next following section D.
D. Detailed Description of the HPSU Block Diagram
The block diagram of the present invention of a High Performance Storage
Unit (HPSU) is shown in FIG. 1, consisting of FIG 1a and FIG. 1b. The HPSU
supports input and output interfaces to and from ten requestors: from and
to Scientific Processor 0 (SP0) respectively across cables 200 and 224,
from and to Scientific Procressor 1 (SPl) respectively across cables 201
and 225, from and to four Input Output Processors (IOP 0-IOP 3)
respectively across cables 202 and 226, and from and to four Instruction
Processors (IP0-IP3) respectively across cables 203 and 227. The HPSU
contains eight storage memory banks, STORAGE MEMORY BANK 0 40a through
STORAGE MEMORY BANK 7 40h, each containing 512K words for a total of 4M
36-bits words of memory storage. Remaining parts of the HPSU shown in FIG.
1 are the data and control paths, and the logic structure, which does
support of the interface of the ten requestors to the eight storage memory
banks.
Considering first the data interfaces to the Scientific Processors - the
data input from SP0 via cable 200b and output to SP0 via cable 224 plus
the data input from SP1 via cable 200b and output to SP1 via cable 225--
such interfaces are uniformly four data words in width. Such four data
words are transferable, bank priority conflicts and pending requests
permitting, at an interface cycle time of 30 nanoseconds. Additionally
received upon cables 200b and 201b, respectively from SP0 and SP1, is
addressing and function information. There are 144 data lines in cables
200b and 201b plus 16 accompanying parity bits. There are also 6
function/write enable lines plus accompanying 1 parity bit. These 6 lines
consist of 2 lines (2 bits) for function and 4 lines (4 bits) for the
master word write enables (corresponding to the 4 words) plus 1
accompanying parity line (bit). There are also 22 address lines (allowing
addressing at four-word boundaries within the collective storage memory
banks, STORAGE MEMORY BANK 0 40a through STORAGE MEMORY BANK 7 40h. The
requests of the HPSU by respective SP0 and SP1 is caried on respective
interface communication lines 200a and 201a. The output cables 224 225
carry four words or 144 bits of read data, plus 16 parity bits.
Continuing in FIG. 1 with the interfaces to the HPSU, the HPSU supports of
four "data"0 interfaces from and to four IOP's, IOP0 through IOP3, on
respective cables 202b and 226. The interface to each IOP is two 36-bit
words in width. Such two words may be transferred to such IOP's
collectively at rates as fast as two words each 120 nanoseconds, and to an
individual IOP at a rate of two words per 300 nanoseconds. Such slower
rate to an individual IOP exists because of communication times across the
interface. There are 72 data lines plus 8 accompanying parity lines in
each of the cables 202b as receive communication from each IOP. There are
additionally 24 address lines plus an accompanying 4 parity lines within
the cables 202b communication path from each IOP. The greater number of
address lines (24) upon the IOP ports than upon the SP ports (22) allows
of addressing at the word boundaries within the collective storage memory
banks. Finally, each IOP interface upon cables 202b carries 5 function
lines plus an accompanying 1 parity line, and 12 lines carrying the
start/end bits plus an accompanying 2 parity lines. The request signals
from each of up to four IOP's are received via a dedicated line for each
upon cable 202a. Each of the output cables 226 to each of the four IOP's
carries 72 bits of read data, plus an accompanying 4 parity bits, on 80
total lines.
Likewise to the interface to the IOP's, the HPSU block diagrammed in FIG. 1
supports of an interface to four Instruction Processors, or IP's: the
receipt of data and address and function and start/end information from
the IP's which transpires on cable 203b, the receipt of requests from the
IP's which transpires on cable 203a, and the issuance of data to the IP's
which transpires via cable 227. The width of each data transfer is two
words. The rate of data transfer may be as great as eight words per 240
nanoseconds for the IP's collectively during the block read operation
thereto. For normal, non-blocked, read, the data transfer rate is
identical to the IOP's at two words per 1 | | |
