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Claims  |
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What we claim is:
1. An adaptive noise canceller, comprising:
first means for receiving a primary signal having a first desired portion
and a second undesired noise portion;
second means for receiving, during each of a successive sequence of time
intervals (n); a reference signal (r(n)) having a first crosstalk portion
with a time-amplitude characteristic similar to that of said primary
signal first portion and a second noise portion with a time-amplitude
characteristic similar to that of said primary signal second portion;
first summer means for subtracting from said primary signal, received from
said first means, a noise reference signal (w(n)) to provide an output
signal (S(n)) having said primary signal first portion and a second
undesirable noise portion which is of reduced amplitude with respect to
the amplitude of the primary signal second portion;
first adaptive filter means having a reference input receiving said
reference signal (r(n)) from said second means, a first error-control
input receiving said output signal (S(n)), and a second error-control
input receiving an estimation signal (S.sub.1 (n)), for providing said
noise reference signal (w(n)) responsive to a predetermined response
pattern dependent upon the conditions of all of said signals then present
at said reference input, said first error-control input and said second
error-control input;
second adaptive filter means having a reference input receiving said output
signal (S(n)) and a single error-control input receiving an auxiliary
signal (w.sub.1 (n)) for providing said estimation signal (S.sub.1 (n)) to
said first adaptive filter means second error-control input; and
second summer means for subtracting said estimation signal (S.sub.1 (n))
from said reference signal (r(n)) to provide said auxiliary signal
(W.sub.1 (n)) to said second adapter filter means signal error-control
input.
2. The adaptive noise canceller of claim 1, wherein said first adaptive
filter means provides said noise-reference signal (w(n)) responsive to a
set of filter coefficients (b.sub.k (n+1)), where k is each integer number
between zero and a number N of equivalent first filter taps, said filter
coefficient set being periodically modified both by the output signal
(S(n)) at said first error-control input and by said estimation signal
(S.sub.1 (n)) at said second error-control input.
3. The adaptive noise canceller of claim 2, wherein the coefficients
b.sub.k (n+1) of said first adaptive filter coefficient set are
periodically modified in accordance with the formula:
b.sub.k (n+1)=b.sub.k (n)+2.mu.S(n)[r(n-k)-S1(n-k)]
where .mu. is a first small positive step-size constant.
4. The adaptive noise canceller of claim 3, wherein said second adaptive
filter means provides said auxiliary signal (w.sub.1 (n)) responsive to
another set of filter coefficients c.sub.k' (n+1), where k' is each
integer number between zero and a number N' of equivalent second filter
taps, said another filter coefficient set being periodically modified by
said auxiliary signal (w.sub.1 (n)) at said single error-control input.
5. The adaptive noise canceller of claim 4, wherein the number N of
equivalent first filter taps is substantially equal to the number N' of
equivalent second filter taps.
6. The adaptive noise canceller of claim 4, wherein the coefficients
c.sub.k (n+1) of said second adaptive filter coefficient set are periodic
modified in accordance with the formula:
c.sub.k' (n+1)=c.sub.k' (n)+2.mu.'[r(n)-S.sub.1 (n)].multidot.S(n-k')
where .mu.' is a second small step-size constant.
7. The adaptive noise canceller of claim 6, wherein said first constant
.mu. is substantially equal to said second constant .mu.'.
8. The adaptive noise canceller of claim 6, wherein said second adaptive
filter means comprises a finite-impulse-response filter having a delay
line of N' taps.
9. The adaptive noise canceller of claim 1, wherein said second adaptive
filter means provides said auxiliary signal (w.sub.1 (n)) responsive to a
set of filter coefficients c.sub.k' (n+1), where k' is all integer numbers
between zero and a number N' of equivalent second filter taps, said filter
coefficient set being periodically modified by said auxiliary signal
(w.sub.1 (n)) at said single error-control input.
10. The adaptive noise canceller of claim 9, wherein the periodic
modification of the set of second adaptive filter coefficients c.sub.k
'(n+1) is in accordance with the formula:
c.sub.k' (n+1)=c.sub.k' (n)+2.mu.'[r(n)-S.sub.1 (n)].multidot.S(n-k')
where .mu.' is a small step-size constant.
11. The adaptive noise canceller of claim 10, wherein said second adaptive
filter means comprises a finite-impulse-response filter having a delay
line of N' taps.
12. An adaptive noise canceller, comprising:
microcontroller means for processing digital signals, said microcontroller
means comprising at least a central processing unit and a plurality of
register sets each containing at least one storage register of at least
one storage location and at least two storage register sets for storing
first and second adaptive filter coefficient sets b.sub.k and c.sub.k each
having at least one coefficient term therein;
first means, receiving from a first transducer a primary input analog
signal, containing a first desired signal portion and a second undesired
random noise signal portion and having a first ratio of the amplitudes of
the desired signal to the noise signal, for converting said primary analog
signal to a digitally-encoded primary signal at a rate responsive to at
least one clock signal;
second means, receiving from a second transducer, different from said first
transducer, a reference input analog signal, having a first crosstalk
signal portion with a time-amplitude characteristic similar to that of
said first portion of said primary signal and having a second random noise
portion with a time-amplitude characteristic similar to that of the second
portion of said primary signal and having a crosstalk signal to noise
signal amplitude ratio independent of the first ratio of the primary input
analog signal, for converting said reference analog signal to a
digitally-encoded reference signal at a rate responsive to said at least
one clock signal;
clock means for providing said first and second converting means with said
at least one clock signal;
memory means for storing a sequence of digital control signals to be
sequentially provided to said microcontroller means responsive to requests
therefrom, and for causing: (a) said microcontroller means to alternately
obtain for storage in first and second register sets, respectively, the
digitally-encoded primary and reference signals, respectively, from the
respective first and second converting means; (b) to cause said
microcontroller means to obtain, for storage in a third register set, at
least one digital signal estimating the crosstalk speech portion in said
reference signal; (c) for causing said microcontroller means to obtain,
for storage in a fourth register set, at least one other signal estimating
the noise portion of said reference signal; and (d) for causing said
microcontroller means to then obtain, from the data in at least said first
through fourth register sets and said first and second coefficient
register sets, an output signal, for storage in a fifth register set,
having the desired signal portion of said primary input and said second
undesired portion of said primary input reduced in amplitude responsive to
the reference signal noise portion estimation signal; and
means receiving the reduced-noise-portion output signal from said fifth
register set for providing a canceller output signal.
13. The adaptive noise canceller of claim 12, wherein said first means
further comprises CODEC means for selectively filtering and then
digitally-encoding, responsive to said at least one clock signal, said
primary input analog signal.
14. The adaptive noise canceller of claim 13, wherein said CODEC means
provides the digitally-encoded primary input signal as a serial data
output signal having a series of sequential data bits.
15. The adaptive noise canceller of claim 14, wherein said microcontroller
means has at least one parallel-data input port, said first means further
including: means for converting the serial data output signal from said
CODEC means to a parallel digital data format for introduction to said at
least one data input port of said microcontroller means.
16. The adaptive noise canceller of claim 12, wherein said second means
further comprises CODEC means for selectively filtering and then
digitally-encoding, responsive to said at least one clock signal, said
reference input analog signal.
17. The adaptive noise canceller of claim 16, wherein said CODEC means
provides the digitally-encoded primary input signal as a serial data
output signal having a series of sequential data bits.
18. The adaptive noise canceller of claim 17, wherein said microcontroller
means has at least one parallel-data input port, said second means further
including: means for converting the serial data output signal from the
CODEC means to a parallel digital data format for introduction to said at
least one data input port of said microcontroller means.
19. The adaptive noise canceller of claim 12, wherein said microcontroller
means has at least one parallel-data output port and said output means
further includes: means, receiving said output signal as a set of parallel
data signals from said microcontroller output port, for converting said
parallel digital data signals to a serial data bit stream which is
provided as said canceller output signal.
20. The adaptive noise canceller of claim 12, wherein said memory means
comprises: read-only memory (ROM) means having said digital control
signals stored therein, but incapable of sequentially providing said
digital control signals at a desired sequential rate responsive to
requests therefor from said microcontroller means; random-access memory
(RAM) means capable of providing said digital control signals at the
desired sequential rate to said microcontroller means responsive to
requests therefrom; and means for transferring the digital control signals
stored in said ROM means to said RAM means upon commencement of operation
of said adaptive noise canceller.
21. The adaptive noise canceller of claim 20, wherein said transferring
means comprises: means for providing to said microcontroller means a first
clock frequency, less than a desired microcontroller operating frequency
at which the digital control signals are at said desired sequential rate,
to cause said ROM means to be accessed at a first rate at the commencement
of operation of said canceller and during transfer of the entirety of the
digital control signals from said ROM means to said RAM means, and for
then providing an operating clock frequency, greater than the first clock
frequency, to said microcontroller means thereafter, to cause said digital
control signals now stored in said RAM means to be provided to said
microcontroller means responsive to requests therefrom, at a higher rate
of transfer than possible from said ROM means.
22. The adaptive noise canceller of claim 21, wherein said clock means also
provides said first clock frequency signal and said higher clock frequency
signal.
23. The adaptive noise canceller of claim 12, wherein each of said at least
two register sets for storing said first and second adaptive filter
coefficient sets b.sub.k and c.sub.k store a predetermined number of
coefficients sufficient to implement the equivalent of a
finite-impulse-response filter having a preselected plurality of delay
means taps.
24. The adaptive noise canceller of claim 23, wherein each of the first and
second filter coefficient register sets stores a number of coefficients
sufficient to implement a 16-tap delay-line filter.
25. The adaptive noise canceller of claim 12, wherein: the first
coefficient set storage register stores the set of first coefficients
b.sub.k (n), where k is each integer number between zero and a
predetermined number N of equivalent first filter tops and n is one of a
successive sequence of time intervals; and the microcontroller means is
caused to periodically modify, during each time interval n, the set of
first coefficients b.sub.k (n) to a set of first coefficients b.sub.k
(n+1) in accordance with the formula
b.sub.k (n+1)=b.sub.k (n)+2.mu.S(n)[r(n=k)-S1(n-k)]
where .mu. is a first small positive step-size constant, S(n) is output
signal data provided from the fifth register set, r(n-k) is reference
signal data provided from the second register set, and S1(n-k) is
crosstalk speech portion data provided from the third register set. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
The present application relates to adaptive noise cancellers and, more
particularly, to a novel two-input adaptive noise canceller which is
resistant to crosstalk between the primary signal and reference noise
inputs.
Dual-input adaptive cancellers are known to the communication arts. Many
examples of such apparatus are reviewed by B. Widrow et al. in "Adaptive
Noise Cancelling: Principles and Applications", Proc. IEEE, Vol. 63, Pages
1692-1716 (December 1975). This review article particularly illustrates
the use of least-mean-square (LMS) gradient control algorithms, generally
accepted to originate with Widrow.
PRIOR ART
Widrow's adaptive canceller 10 is illustrated in FIG. 1. The primary input
10a receives a signal which has both a desired signal component S(n),
which may be a speech signal and the like, and a noise component w(n). The
reference input 10b receives a reference signal r(n) which is assumed to
be correlated to the noise signal w(n). Primary input 10a is connected to
the additive+input 11a of a summer means 11, while a subtractive--input
11b thereof receives an input noise-component-related signal w(n); the
difference between the primary input signal and the signal w(n) appears at
output 11c of the summer means and provide the canceller output signal
S(n) at output 10c. An adapter filter means 12 receives the reference
input signal r(n) at a main, or reference, input 12a and receives the
canceller output signal S(n) at a control, or error, input 12c for
providing the w(n) signal at the adapter filter means output 12b.
One possible implementation of adapter filter means 12 is shown in FIG. 1a.
The reference input 12a is connected to the input 14-0 of a tapped delay
line 14, having a plurality N of taps 14-1 through 14-N. The signal at the
delay line input and at each of the delay taps k', where k'=1, 2, 3, . . .
, N provides a different one of the N+1 individual, increasingly-delayed,
signals r(n), r(n-1), . . . , r(n-N) for connection to the associated one
of inputs 16-0a, 16-1a, 16-Na of N+1 gain-controlled amplifiers 16-0
through 16-N. The signals at the N+1 outputs 16-0b, 16-1b, . . . , 16-Nb
of the amplifiers is the product of the input signal r(n-k), where k=0, 1,
2, . . . , N, and the individual amplifier gain b.sub.0, b.sub.1, . . . ,
b.sub.N, where the individual amplifier gain b.sub.k is set for each
amplifier responsive to the signal received at a gain-control input 16-0c,
16-1c, . . . , 16-Nc. The gain control signal at each input 16c is
established at the output 18a of a least-mean-square (LMS) control means
18, having a first input 18b receiving the canceller output signal S(n)
from error input terminal 12c, and a second input 18c, receiving the
reference input r(n) signal from input 12a. Control means 18 implements
the stage gain b.sub.k in each time interval m=(n+1) in accordance with
the formula: b.sub.k (n+1)=b.sub.k (n)+2.mu.S(n).multidot.r(n-k), where
.mu. is a small, positive step-size constant. The output 16-kb of each
amplifier is connected to an associated one of the N+1 inputs 20-0, 20-1,
. . . , 20-N of a N+1 input summer means 20, having an output 20a
providing the adaptive filter means output signal w(n) to the adapter
filter means output terminal 12b.
For this particular two-input adaptive canceller apparatus, Widrow has
shown theoretical results for a converged, unconstrained Weiner filter in
the presence of crosstalk, but this algorithm fails to converge under
these conditions. Thus, Widrow's LMS gradient canceller, as with other
classical two-source adaptive cancellers, requires that the reference
input signal r(n) be a noise signal which is highly correlated with the
noise signal portion w(n) of the primary input signal (which primary input
signal is a combination of a desired, typically speech, signal portion and
a noise signal portion) but which reference noise signal is substantially
uncorrelated with the desired (speech) signal at the primary input. If the
desired (speech) signal is present not only at the primary input but is
also introduced into the reference input, the crosstalk condition obtains
and the LMS gradient algorithm used to set the adaptive filter taps will
no longer converge to the optimum solution; the system output
signal-to-noise ratio will be degraded. In a practical situation, such as
in mobile communications where the primary and reference input microphones
are both located in the passenger compartment of the same automobile, it
is extremely difficult to obtain a speech-free reference noise signal.
It is therefore highly desirable to provide a two-input adaptive noise
canceller which will not experience serious degradation in its output when
the desired (speech) signal is present in both the primary and reference
noise input channels.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a two-input crosstalk-resistant
adaptive noise canceller, having a primary input signal including a
desired speech signal portion and an undesired noise signal portion, and
also having a reference input signal having a reference noise input
portion and a crosstalk speech portion, comprises first and second summer
means and first and second adaptive filter means. The first summer means
provides a canceller output signal which is the difference between the
primary input signal and the first adaptive filter means output signal.
The canceller output signal is applied to the reference input of the
second adaptive filter means and to one of a pair of error-control inputs
of the first adaptive filter means. The second error-control input of the
first adaptive filter means is provided by the signal at the output of the
second adaptive filter means, which receives a single error-control input
signal from the output of the second summer means. The second summer means
provides an output signal which is the difference between the reference
input signal and the second adapter filter means output signal. Thus, a
second adaptive filter is utilized to estimate the crosstalk (i.e. the
amount of desired signal at the reference input) portion present in the
reference noise signal, such that the crosstalk portion is then subtracted
from the reference input signal to eliminate errors in the two-input first
adaptive filter means due to estimation bias. With the correlation bias
between the desired primary input (speech) signal and the crosstalk
(speech) signal in the reference input substantially reduced, the
canceller output signal is then related substantially only to the primary
input desired signal.
In a presently preferred embodiment of our novel two-input
crosstalk-resistant automatic noise canceller, a digital-signal-processing
microcontroller is utilized, along with associated read-only memory means
and random-access memory means, to digitally process the primary input and
reference input signals in accordance with a set of first and second
adaptive filter means coefficients b.sub.k and c.sub.k, respectively. The
analog primary and reference input signals are each first converted from
analog to digital serial signals, and are then converted from digital
serial signals to digital parallel signals, for rapid processing in the
digital-signal-processing means. The processed signal is provided as a
serial data output signal S(n) in which the correlation bias between the
crosstalk speech signal in the reference input and the primary speech
input signal is substantially reduced.
Accordingly, it is an object of the present invention to provide a novel
two-input automatic noise canceller which is substantially crosstalk
resistant.
This and other objects of the present invention will become apparent upon
consideration of the following detailed description of our invention, when
read in conjunction with the drawings.
BRIEF SUMMARY OF THE DRAWINGS
FIG. 1 is a block diagram of a prior art two-input adaptive canceller;
FIG. 1a is a block diagram of a finite impulse response filter usable for
providing the adapter filter means of the prior art canceller of FIG. 1,
and controlled in accordance with the Widrow LMS gradient algorithm;
FIG. 2 is a block diagram of our novel two-input crosstalk-resistant
adaptive noise canceller in accordance with the principles of the present
invention;
FIG. 2a is a block diagram of a presently preferred
digital-signal-processing embodiment of the novel automatic noise
canceller of FIG. 2;
FIG. 3 illustrate the manner of joining the first, second and third diagram
portions of FIGS. 3a-3c to provide a detailed schematic diagram of the
circuitry for the presently preferred digital-signal-processing embodiment
of our two-input crosstalk-resistant adaptive noise canceller;
FIG. 4 is a block diagram illustrating the central processing unit (CPU)
and the various working and constant register sets utilized in the
digital-signal-processing microcontroller of the embodiment of FIGS. 2a
and 3a-3c, and useful in understanding operation of the presently
preferred embodiment;
FIG. 5 is a flow chart illustrating the signal processing steps carried out
in one program configuration utilized with the presently preferred
adaptive noise canceller embodiment;
FIG. 6 is a block diagram of a test set-up for providing the signal
photographs of FIGS. 6a-6c; and
FIGS. 6a-6c are portions of a photograph of the primary input, reference
input and output signals simultaneously observed for a two-input
crosstalk-resistive adaptive noise canceller preferred embodiment,
illustrating the crosstalk-resistance thereof.
DETAILED DESCRIPTION OF THE INVENTION
Referring now to FIG. 2, our novel two-input crosstalk-resistant automatic
noise canceller 30 has a primary input terminal 30a receiving a primary
input signal which contains a desired speech signal S(n) portion and an
undesired primary input noise signal w(n) portion. A reference input
terminal 30b receives a reference input signal r(n) which comprises a
reference noise input signal w.sub.1 (n) portion and a speech crosstalk
signal S.sub.1 (n) portion. Automatic noise canceller 30 provides an
output signal terminal 30c with an output signal S(n) which is closely
related to the desired primary speech input signal S(n) and from which the
noise input signal w(n) portion has been substantially removed, without
correlation bias due to the speech crosstalk signal S.sub.1 (n) portion
which is unavoidably present at reference input terminal 30b.
Adaptive noise canceller 30 utilizes a first summer (.SIGMA.) means 31
having a first, additive+input 31a receiving the primary input signal from
primary input terminal 30a. First summer means 31 has a second,
subtractive--input 31b receiving an adaptively-filtered reference noise
signal w(n) from the output 32a of a first adaptive filter means 32,
having a reference input 32b connected to reference input terminal 30b.
The output 31c of first summer means 31 provides an output signal S(n) to
the canceller output terminal 30c. The first summer means output 31c is
also connected to a first error-control input 32c of the two-control-input
first adaptive filter means 32, and to the reference input 34a of a
single-control-input second adaptive filter means 34. The output 34b of
second adaptive filter means 34 provides a signal S.sub.1 (n), which is an
estimate of the speech signal (i.e. the crosstalk) present in the
reference input at terminal 30b, for providing a second error-control
signal to a second error-control input 32d of first adaptive filter means
32. The second adaptive filter means single error-control input 34c
receives a control signal w.sub.1 (n). This w.sub.1 (n) signal is provided
at the output of a second summer (.SIGMA.) means 36, having a first,
additive + nput receiving the reference input terminal 30b reference
signal r(n) and having a second, subtractive - input 36b receiving the
output signal S.sub.1 (n) from output 34b of the second adaptive filter
means. Thus, the second summer means output 36c estimates the noise
portion of the reference input.
Second adaptive filter means 34 may be a finite-impulse-response (FIR)
filter utilizing a tapped delay line and of the form shown in FIG. 1a,
where the second adaptive filter coefficients c.sub.k (n+1) are updated in
accordance with the formula:
c.sub.k (n+1)=c.sub.k (n)+2.mu.[r(n)-S.sub.1 (n)].multidot.S(n-k) (1)
for k=0, 1, . . . , N (the number of filter delay line taps), and .mu. is a
small positive step-size constant. First adaptive filter means 32 can also
be an FIR filter, having a two-error-signal-input control means 18 (see
FIG. 1a) for establishing the first adaptive filter coefficients b.sub.k
(n+1) responsive to both the feedback signal S(n) at first control input
32c and the feedback signal S.sub.1 (n) at second control input 32d, so
that
b.sub.k (n+1)=b.sub.k (n)+2.mu.S(n)[r(n-k)-S1(n-k)]. (2)
The foregoing equations (1) and (2) assume that the step-size constants
.mu. of both adaptive filter means 32 and 34 are essentially the same and
that both adaptive filter means 32 and 34 are implemented with a tapped
delay line having the same number k=N of taps. It will be understood by
those skilled in the art that the single-control-input second adaptive
filter means 34 can equally as well have a different step-size constant
.mu.' and/or a different number of delay line taps N' from the step-size
constant .mu. and the number N of delayed input signals provided for the
double-control-input first adaptive filter means 32.
While the crosstalk-resistant two-input automatic noise canceller 30 of
FIG. 2 can be assembled with analog circuitry, utilizing analog forms of
adaptive filter means (such as the FIR filter means of FIG. 1a and the
like), the resulting canceller would be relatively bulky, due to the
volume required for implementation of 2(N+1) analog amplifiers, a pair of
tapped delay lines, a pair of (N+1) input analog summer means 20 (in
addition to the dual input analog summer means 31 and 36), and the
single-control-input and dual-control-input LMS control means for the
first and second adaptive filters, respectively. We therefore prefer to
convert the pair of input analog signals to a pair of digital signals and
to provide not only the two adaptive filtering functions but also the two
summing functions in a digital-signal-processing microcontroller, in the
digital automatic noise canceller 30' of FIG. 2a.
The digital automatic noise canceller 30' utilizes a
digital-signal-processing means 40 which has a first port 40a for driving
an address (ADDX) bus 41. Address bus 41 has a plurality L of parallel
lines, of which at least a somewhat smaller plurality L1 of lines form an
extension 41a of the ADDX bus into a read-only memory means 42. The
digital-signal-processing (DSP) means 40 illustratively has a serial data
output 40b, connected to the digital automatic noise canceller apparatus
output terminal 30'c. An input/output (I/O) terminal 40c receives a signal
from the output 44a of a multiplexer means 44 determining which one of
respective first frequency (CLK1) clock and second frequency (CLK2) clock
signals, respectively provided to multiplexer inputs 44b and 44c, is
provided to output 44a, responsive to the state of a signal at a control
input 44d. DSP microcontroller means 40 has a data but port 40d, having a
plurality M of parallel signal lines for carrying data into and out of the
digital-signal-processing means, as from program memory means 42 and the
like. The memory means output is enabled by an output enable OE signal
provided at the memory enable (MEN) output 40e of the DSP. A decoder
enable (DEN) output 40f is provided to a control input 46a of a decoder
means 46, also receiving a plurality of L2 of the ADDX bus lines in
another address bus extension 41b to a decoder data input port 46b.
Dependent upon the state of the DEN signal and the signals on the L2 lines
of ADDX bus extension 41b, either one, but not both, of decoder means
first output 46c or second input 46d may be enabled at a particular time.
Output 46c is utilized to enable the primary input digital data, in
M-bit-parallel digital format, to travel along data bus 43 to DSP data
port 40d, while decoder means output 46d enables the M-bit-parallel
digital representation of the reference channel signal along data bus 43
to DSP port 40d.
The primary and reference signals originate with a pair of transducer means
48 and 49, such as microphones and the like, respectively providing analog
signals to the primary input terminals 30'a and to the reference input
terminals 30'b of the adaptive noise canceller (ANC) 30'. Primary signal
input 30'a is connected to the analog input terminal 50a of a first
analog-to-digital conversion, or CODEC, means 50. Simultaneously, a second
analog-to-digital conversion, or CODEC, means 52 has the analog input 52a
thereof provided with the reference analog signal from terminal 30'b. A
clock means 54 provides master clock frequency F.sub.f signals to both
first clock inputs 50b and 52b, framing clock frequency F.sub.F signals to
both second clock inputs 50c and 52c, and encoding clock frequency F.sub.d
signals to both third clock inputs 50d and 52d of CODEC means 1 and 2.
Each of CODEC means 1 and 2 filters, compands and digitally encodes
samples of the input analog signal, in accordance with a companded
.mu.-law format. The .mu.-law serial-digital-encoded primary signal or
reference signal is respectively provided at the CODEC 1 means output 50e
or the CODEC 2 means output 52e, respectively. The serially-encoded
digital primary signal appears at the serial input 56a of a first
serial-to-parallel conversion (shift register) means 56, which receives
the third frequency F.sub.d clock signal at a clock input 56b and also
receives the primary channel enabling ADDX O signal at an input 56c, from
decoder means output 46c, to provide an M-bit parallel-formatted digital
signal at shift register 1 means output 56d, to data bus 43. The
serially-encoded digital reference signal appears at the serial input 58a
of a second serial-to-parallel conversion (shift register) means 58, which
receives the frequency F.sub.d clock signal at a clock input 58b and also
receives the reference channel enabling signal ADDX1 at an input 58c, from
decoder means output 46d, to provide another M-bit parallel-formatted
digital signal from shift register 2 means output 58d, to data bus 43.
Since the ADDX 0 and ADDX 1 signals appear in mutually-exclusive manner,
only one of outputs 56d and 58d provides data to bus 43 at any particular
time. If ANC 30' is utilized with a communications transceiver, the
digitally-encoded received data can be converted to analog form by use of
DSP means 40, in conjunction with a parallel-to-serial conversion (shift
register) means 58', which can be formed from the second
serial-to-parallel conversion (shift register) means 58 if a programmable
serial-to-parallel/parallel-to-serial shift register means, such as a
standard 74HC595 integrated circuit and the like, is utilized therefor.
Thus, the processed parallel digital signal received at a parallel input
58'b can be changed, responsive to the presence of a receive-mode WE
signal at another control input 58'e, to provide a serially-encoded
digital signal at serial output 58'a. This signal can be introduced into
an incoming-signal input 52f of CODEC means 52, and then be
reverse-converted from digital to analog format, such that the received
signal appears in analog form at CODEC means 2 output 52g and at a
terminal 30'f of the ANC apparatus. The analog signal can be further
amplified by an audio frequency AF amplifier means 60 and provided to a
transducer means 62, such as a loudspeaker and the like.
Referring now more specifically to FIGS. 3a-3c, arranged as shown in FIG.
3, and to FIG. 4, the DSP microcontroller means 40 "(FIG. 4)" must have a
central processor unit 40-1 capable of processing the parallel M-bit
digital signals provided at the primary signal input port P0 or the
reference signal input port P3, with sufficient speed to provide the
adaptive-noise-cancelled serial output signal (SIG) at terminal 40b. DSP
means 40 also must have at least five working register sets denominated
as: primary (PRIM) register set 40A; reference (R) register set 40B; W(n),
or (FREF), register set 40C; output signal (S-HAT) register set 40D; and
adaptive filter means 2 output (S1HAT) register set 40E; in addition to
register sets 40F and 40G for respectively storing the first adaptive
filter means (B) constants and the second adaptive filter means (C)
constants. All of register sets 40A-40G work in conjunction with the CPU
40-1, under control of the program-control memory means 42, in manner to
be described hereinbelow. Storage means 40A-40G are each referred to as a
"register set", rather than as a sing | | |
