An integrated memory circuit includes a memory loop which comprises two gates which are controlled by a clock signal. The circuit is susceptible to a race condition so that correct operation cannot always be ensured. The "race" problem is solved by choosing the switching thresholds of the gate inputs receiving the clock signal so that the gates respond successively instead of (sustantially) simultaneously to the clock signal. The correct switching sequence of the gates and the correct operation of the memory circuit can thus be ensured.

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

The present invention is an interface adapter circuit that allows multiple types of 256K by 16 bit dynamic random random access memories to be used by system manufacturers. The interface adapter circuit selects a type of outputs signal set to produce responsive to a mode selection signal. The circuit converts an input signal set including a column address probe and low and high by write signals into either a first output signal set, including one column address strobe and high and low byte write signals, or a second output signal set including a single write signal and high and low column address signals, responsive to the selection signal. The circuit includes a logic circuit for producing the signals and flip flops for holding the signal produced. The flip flops also synchronize other memory address, etc. signals with the signals produced by the adapter circuit. The interface adapter circuit can also convert write nd column address timing signals and low and high byte write signals into the two sets responsive to a selection signal.

A system for refreshing dynamic random access memory that does not request the bus from the CPU prior to performing a refresh operation. The system initiates a refresh operation when the end of a CPU bus cycle is signalled and stores status and address data if the CPU initiates a new CPU bus cycle prior to the completion of the refresh operation.

A video signal circuit performing the function of time base correction has a pair of memories each adapted to store at least one field of video data and a pair of shift registers associated with both memories. The memories are set to the read state and write state alternately. A shift register associated with a memory in its write state receives one unit of video signal data in series in response to a first sync signal to write these data in the associated memory during a portion of the horizontal blanking period specified by the first sync signal. The other shift register associated with the memory in its read state reads another unit of video signal data from the associated memory during a portion of the horizontal blanking period specified by a second sync signal to sequentially produce the read data in synchronism with the second sync signal.