An interface unit for connecting a transmitting unit to a receiving unit, the transmitting being capable of transmitting data at a speed greater than the processing speed of the receiving unit. The interface includes a serially connected multistage register which receives input data from the transmitting unit at its input stage and reads out data stored in its output stage to the receiving unit. It also includes a control circuit and a counter storing a count corresponding to the quantity of data stored in the register, the counter being incremented by one each time data is added to the register and decremented by one each time data is read from the register output stage. The control circuit is composed of a decoder and write control circuit. The decoder provides a signal to the write control circuit indicative of the count in the counter. When a datum is to be received from the transmitting unit, it signals the interface through a gate circuit, this signal incrementing the memory. This increment is sensed by the decoder which enables the write control circuit to cause the input data to be written into the first available register stage closest to the output stage. When the register is full, this information is provided to the transmitting unit by the decoder to inhibit the generation of additional data to the interface until an empty stage is available in the register.
An interface circuit connected between first and second units includes first and second registers, wherein these first and second units are asynchronous with each other. Data from the first unit is written into the first register by a write pulse from the first unit, while the output of first register is to be read by the second register by a read-in pulse from the second unit. This write pulse is asynchronous with the read-in pulse. When a phase difference between phases of the write pulse and read-in pulse is within the predetermined phase range, the phase of read-in pulse is varied by the predetermined phase value, e.g., 180 degrees. Then the second register reads in the output of first register by this read-in pulse whose phase is varied. Thereafter, the output of second register is fed to the second unit, so that the data transfer is performed between the first and second units without data dropout.
A serial input interface circuit includes a shift register connected to a data input terminal, a parallel register coupled via an output buffer to a data bus, a parallel register empty flag and a serial input suspension request flag which can be set, at any time during progress of input processing of input serial data into the shift register even while the parallel register empty flag is reset to indicate absence of parallel data in the parallel register and consequently even while the input serial data are supplied into the shift register, by a program for controlling transfer, to the data bus, of the parallel data which are stored in the parallel register when a predetermined transfer bit length of the input serial data is stored in the shift register. Setting of the serial input suspension request flag sets, in turn, a serial input suspension carry out flag immediately when the parallel register empty flag is reset. This prevents a serial input request signal generating circuit from producing a serial input request signal which would otherwise be produced to continue the input processing when the transfer bit length of the input serial data is stored in the shift register for delivery to the parallel register.
An interface system for use with an electronic computer including a CPU, a main memory, an input/output channel unit to which a group of latches is connected by a ring transmitting path and adapted to serve as a serial register, and a service processing unit including an operator's console control unit for performing a resetting operation or the like for each of such units, wherein the service processing unit affords read/write operations of data transmitted from the serial register by itself, and which is characterized by an additional console shift register provided in the input/output channel unit, which allows an interface to be implemented between the input/output channel unit and the operator's console control unit by the reading/writing of data into and from the console shift register.
A register device is provided with a plurality of sub-register devices. The plurality of sub-register devices are grouped into three sub-register device groups, with a signal processing unit constituted of inverters and a capacitative element provided between adjacent sub-register device groups. A transfer signal output by a transfer signal generator is amplified at the signal processing units. This structure achieves an accurate and efficient transfer of data within the sub-register devices from write register units to read register units.
A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when the neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.
