Test connectors connect a circuit tester to an electronic device to be tested. The test vector matrix is divided into segments, each segment including one or more columns of the matrix. The unique vector segments within each matrix segment are stored in RAMs, one RAM for each test connector. A driver/comparator applies an electrical signal to some of the test connectors in response to a signal received from its associated RAM and receives an electrical signal on other of the test connectors and compares it to a signal received from the RAM. There is an independent sequencer for each matrix segment, each sequencer addressing the RAMs for that segment. A clock initiates and clocks the sequencers in synchrony to produce the test on the test connectors from the unique test vector segments stored in the RAMs.

A semiconductor device tester comprises a random data generator, an algorithmic data generator, and a serial data generator. The test data pattern of the data generators are selected and combined to produce test pattern data actually applied to a device under test. At least part of the test data pattern from the algorithmic data generator are applied to one of the random data generator and the serial data generator, which, responsive thereto, produces the random test pattern data or the serial test pattern data.

A test data generator and a test data converter are provided for generating test data words which are allocated to the terminal elements of a card module having electronic components. Dependent on a test program, the test data generator generates one or more test data vectors per test step to be executed. The test data converter generates the test data words from a test data vector or from further test information, and allocates individual bits of a test vector or of the test information to individual terminal elements of the unit under test. The allocation of the individual bits of the test vector or of the test information to the individual terminal elements of the unit under test can be freely set.

A circuit for applying a testing data to a DUT for testing the DUT comprises a buffer memory for receiving and buffering a redundancy-free information as information which is substantially free of redundancy but might also comprise some redundant information to a certain extent, a redundancy memory for storing a redundancy information as information comprising a certain amount of redundancy, and a processing unit for generating the testing data by processing the redundancy-free information in association with the redundancy information. Further, includes a method for applying a testing data to the DUT for testing the DUT includes the steps of receiving and buffering the redundancy-free information, fetching in accordance with the received redundancy-free information the redundancy information, and generating the testing data by processing the redundancy-free information in association with the redundancy information.

This invention relates to electronic circuit testing and more particularly to an apparatus and a method utilizing enhanced test data compression techniques. An electronic circuit or board tester according to the invention includes one tester circuit with a combination of a sequencer and a vector-sequencer-memory per pin. The test-data-sequence to be applied to a pin of a device under test is compressed in order to save memory space.