Spread spectrum correlation receiver

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BACKGROUND OF THE INVENTION

This invention relates to spread spectrum communication systems and, more particularly, to a receiver for such a system which employs correlation detection means.

Spread spectrum communication systems are useful in environments where a high degree of interference may be experienced. One type of wideband or spread spectrum signal processing technique which is frequently used is the so-called pseudo-random noise or pseudo-noise (PN) system. In such a system the baseband carrier is a coded signal utilizing a long string of 1 and 0 data cells which occur in a predictable sequence but which have properties similar to random numbers. To a listener not knowing the code, the cells appear to occur in a random sequence. If the PN code has N cells (bits), the rf 3 db bandwidth of the transmitted signal is approximately N times the information bandwidth. Thus for a data channel having a bit rate of 100 KBS, use of a PN code with 256 bits produces a signal bandwidth of 25.6 MHz.

In the past it has been the practice to demodulate a PN-coded signal by multiplying the received IF component by the known PN code to obtain a cross-correlation function. When a high correlation output was obtained, indicating that the signal had been acquired, means were employed to "track" this desirable correlation state by controlling the times at which subsequent correlation operations were performed on the signal.

This system suffers from the disadvantage that it locks onto and tracks only a single signal component and if multipath components are present they are not detected. Most important, if the receiver happens to lock onto a multipath component rather than the main signal component, loss of synchronization at the receiver is highly likely to occur due to the susceptibility of the multipath to fading. This is particularly true when the transmitter and/or receiver are mobile (e.g., airborne) since the characteristics of the propagation medium are susceptible to relatively rapid change. Frequent loss of synchronization at the receiver is highly disruptive to the system and can result in loss of data unless very low throughput rates are employed.

Furthermore, when this type of receiver is used in a multiple access system where signals from several transmitting sources must be decoded simultaneously, the receiver is capable of locking onto and tracking only one signal at a time. Conferencing capability is thus not fully achievable. "Conferencing" in a communication system is the ability of a listener at a receiver to simultaneously hear the outputs generated by two or more transmitters in the network, such as occurs in a "party line" telephone hookup. Because the receiver in present spread spectrum communication systems locks onto and tracks only a single component of the received signal and excludes received components for which correlation matches occur at different times relative to the tracked signal component, conferencing is impossible unless all transmitters are synchronized to the same time base and are located exactly the same distance-from the receiver. The latter condition, of course, cannot be achieved in a practical environment, particularly one involving mobile transmitters and receivers.

An experimental system known as "RAKE" was developed in the late 1950's as an approach to resolution of the multipath problem. This system employed tapped delay lines and multiple IF correlators for performing essentially two correlations in "parallel", one for detecting "mark" bits and one for detecting "space" bits. Means were provided for integrating correlation outputs in order to realign the main and multipath signals. All of the signal processing is done using IF signals and both phase and amplitude processing was provided. The "mark" and "space" signals were transmitted orthogonally. The response of the "space" correlator to a "mark" received signal is zero, and the response of the "mark" correlator to a "space" received signal is also zero. However, besides requiring the performance of multiple parallel correlation, this system due to its use of delay lines as the basic storage element, required separate IF correlation subsystems for each tap on the delay line.

Consequently, a very large amount of complex correlation circuitry was necessary and use of the system for any kind of mobile or transportable application was impossible. In addition, the detection sensitivity of the "mark" "space" concept is approximately 4 db poorer in performance than can be achieved by coherent processing in the manner described hereinafter.

OBJECTS AND SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide an improved spread spectrum correlation receiver capable of simultaneously tracking and detecting a plurality of time-delayed signal components.

Another object is to provide a spread spectrum correlation receiver of the type described which is capable of implementation in a low cost, compact and rugged circuit package suitable for portable and/or mobile utilization under rugged field conditions.

Another object is to provide a spread spectrum correlation receiver which uses baseband processing and baseband correlators instead of IF delay lines and IF correlators, and which provides system performance which is near-optimum and equal to or better than can be achieved through IF processing.

Still another object is to provide a high speed, inexpensive signal correlation subsystem capable of performing multiple correlations at a very high repetition rate and in essentially real time.

Still another object is to provide a spread spectrum correlation receiver of the type described which is capable of processing audio signals and simultaneously combining signals transmitted from multiple sources in order to provide a conferencing capability.

According to a first aspect of the invention multiple signal correlations are performed at a high repetition rate on a received PN coded signal by a correlation subsystem comprising a plurality of cascaded correlator circuits of the surface charge transistor (SCT) type. The outputs of the multiple correlations are accumulated during a sampling interval and at the end of the sampling interval the accumulated correlation outputs represent a composite of the data messages received during the sampling interval. In the case of a data link, the composite output signal may represent a single message bit which is the sum of a plurality of signal components (including multipath components) representing the same bit. In the case of an audio system, the composite output may represent a total signal made up of individual audio signal samples transmitted from a plurality of sources such that the audio output developed from a train of such accumulated composite signals gives the same effect as the mixing of a plurality of audio inputs into a single audio speaker channel.

In accordance with this aspect of the invention, correlation processing is performed after the received signal has been converted from IF to the baseband level and the baseband signal is represented by two orthogonal components which are processed in separate and independent channels. After processing, the outputs of the baseband channels are combined in a manner which yields an optimum IF signal response. The system tracks each of the baseband signals so that the effects of timevarying multipath signals with differential doppler between the direct and multipath components can be used to enhance system sensitivity. Further, the signals from each of the baseband channels are proportional to the weighted average of the doppler on the direct and multipath components such that they can be used for coarse doppler tracking.

In accordance with a second aspect of the invention, a signal correlation subsystem is provided wherein an N-stage correlation circuit receives and stores input signal samples in a rolling sequence that eliminates any need to transfer samples from stage to stage and allows samples to reside in the same stage until they are replaced by a new sample. In synchronizism with this sample loading sequence the bits of the reference signal are circulated through the stages in shift register fashion such that the last bit of the reference signal remains substantially in alignment with the newest input signal sample and the first bit of the reference signal remains substantially in alignment with the oldest stored signal sample. With this arrangement, N-point correlations are provided for an N-bit reference signal.

These and other objects, features and advantages will be made apparent by the following description of preferred embodiments of the invention, the description being supplemented by drawings as follows:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating one type of environment in which the system of the invention is designed to operate.

FIG. 2a is a block diagram showing the general circuit arrangement of the principal embodiment of the invention.

FIG. 2b is a block diagram illustrating the circuits of the frame sync detector 110 of FIG. 2a.

FIG. 3 is a schematic diagram showing the basic frame, word and bit format for transmitted messages used in connection with the principal embodiment hereinafter described.

FIGS. 4a and 4b, taken together, are a detailed circuit schematic showing a portion of the system of FIG. 2a.

FIG. 5 is a graphic illustration of the sequence in which input signal samples and reference signal samples may be loaded into and shifted through the correlator subsystem of the invention.

FIG. 6 is a schematic diagram depicting an SCT correlator stage as used in the correlator subsystem of the invention.

FIG. 7 is a schematic circuit diagram illustrating a 32-stage correlator circuit.

FIG. 8 is a schematic circuit diagram showing the correlator timing circuits of FIG. 7.

FIG. 9 is a waveform diagram showing the relationship between the basic clock pulses SCLK, SCLK and CCLK used in connection with the circuits of FIGS. 4a, 4b, 7 and 8.

FIG. 10 is a waveform diagram showing the interrelation of the various timing signals used to control the correlator circuits.

FIG. 11 is a circuit schematic showing one stage of the scan bit shift register of FIG. 7.

FIG. 12 is a circuit schematic showing one stage of the reference bit shift register of FIG. 7.

FIG. 13 is a circuit schematic showing the correlator output summing circuits and differential amplifier used with the I channel correlator circuits.

FIG. 14 is a timing diagram illustrating the system operation of the I channel of the principal embodiment of the invention.

FIGS. 15a, 15b, and 15c are waveform diagrams comparing the raw correlation output signals CI.sub.i and CI.sub.i+1 to the smoothed correlation signal FI.sub.i.

FIG. 16 is a waveform diagram illustrating the manner in which PWM audio signal samples are impressed on a PN coded carrier for transmission and decoding in connection with an alternative embodiment of the invention.

FIG. 17 is a block diagram showing the correlator circuits and the basic timing and control circuits used in connection with the audio embodiment of the invention.

FIG. 18 is a schematic circuit diagram showing the adaptive filter arrangement used with the audio embodiment of the invention.

GENERAL DESCRIPTION OF EMBODIMENT

Referring to FIG. 1, a typical operating environment for the system of the invention is depicted. A transmitting station carried in an aircraft 10 is located at a remote distance from the receiver which is contained in a remotely piloted vehicle 12. It is desired to transmit a command signal S from the command station 10 to vehicle 12 in order to provide control data to the latter. In addition, a return signal 13 is generally transmitted from the vehicle 12 back to the command station for the purpose of returning control response data.

The environment confronting the system and the command signal S is very likely to include signal multipath generating elements such as atmospheric thermal inversion layer 14 and body of water 16. Atmospheric discontinuities such as layer 14 are likely to cause components of signal S to be reflected and/or refracted and the body of water 16 is likely to reflect signal components. As a result, the main signal component S1, which propagates directly from the transmitter to the receiver, may be accompanied by additional signal components S2, S3 and S4, known as multipath signals, or simply "multipath", which are reflected and/or refracted versions of the main signal component S1. The multipath components will arrive at the receiver sometime after the main signal component since, as is illustrated in FIG. 1, they traverse longer signal paths.

The multipath components are undesirable since they can interfere with the main signal and cause signal fading and consequent data loss at the receiver. Multipath caused by atmospheric reflection and/or refraction is generally referred to as "atmospheric multipath" and multipath caused by reflection from bodies of water is generally referred to as "specular multipath".

As heretofore described, a technique which has been used to eliminate the adverse effects of multipath involves a technique of correlation tracking of one of the signal components to the exclusion of the others. One of the drawbacks of this approach is that the system may lock onto one of the multipath components rather than the main signal component and when the characteristics of the environment change and the multipath fades, the receiver can lose lock and then has to acquire and lock onto another signal component. Reacquisition of the signal takes time and may result in loss of data at the receiver.

FIG. 2a shows a block diagram of a data communication system constructed in accordance with the principals of the invention. A transmitter 20 includes a data entry circuit 22 which generates binary coded data in accordance with desired command information. A PN code generator 24 generates a sequence of pseudo-noise coded binary reference bits. For example, the PN code bits may be stored in a read only memory (ROM) module and may be read out of the ROM in a desired time sequence. Multiplier circuit 26 combines the PN coded carrier signal from generator 24 with the binary data signal from data entry circuit 22 into a baseband signal BB and the latter is converted by a conventional biphase modulation circuit 28 to an RF wideband signal S. As previously mentioned, 3 db the bandwidth of signal S is N times the information bandwidth, where N is the number of PN code bits in each cell of the message data. Thus, if the data signal from circuit 22 has a frequency of 100 KBS and if PN generator 24 produces 256 carrier bits per message bit, the 3 db bandwidth of signal S is approximately 25.6 MHz.

The transmitted signal may be organized in accordance with the frame, word and bit format shown in FIG. 3. Each data frame may, for example, include eight single bit words, each word spanning 256 bits of the PN code. The latter is also illustrated in FIG. 3. The words may be positioned at the beginning of each data frame and the repetition rate, and thus the period, of the frames is selected in accordance with the desired data thruput rate.

As shown in FIG. 3, the PN carrier signal is a square wave made up of a series of binary bits arranged in accordance with conventional pseudo-random noise code generation techniques. As previously mentioned, the bits of the code occur in a predictable pattern but, for one who does not have knowledge of the generation formula, the bits appear to occur in a random sequence. When modulated (multiplied) by a "1" data bit, (+1 modulation), the PN coded carrier signal is simply a replica of itself. When modulated by a 0 data bit (-1 modulation), the carrier is the inverse of the generated code, as shown in FIG. 3.

Referring back to FIG. 2a, a receiver 100 comprises a conventional synchronous demodulator 102 for converting the input signal into two baseband signals S'I and S'Q. The synchronous demodulator may comprise, for example, an IF converter for converting the received RF signal to an IF signal together with a synchronous detector. The first signal S'I is a signal which contains multiple replicas of the transmitted signal as it appeared at the output of multiplier 26 at the transmitter. Each replica has a delay relative to the first replica "direct signal" and a weighting factor which is dependent on the phase delay of the signal relative to the reference oscillator in the synchronous demodulator.

These signals may be defined as follows:

S'I(t)=S.sub.1 (t-T.sub.1) cos .phi..sub.1 +S.sub.2 (t-T.sub.1 -T.sub.2) cos .phi..sub.2 +S.sub.i (t-T.sub.1 -T.sub.i) cos .phi..sub.i +

where

S'I(t)=in-phase output of the synchronous detector;

S.sub.1 (t-T.sub.1)=direct signal replica of the baseband signal delayed by a time T.sub.1 which is dependent on the range between transmitter and receiver;

S.sub.i (t-T.sub.1 -T.sub.i)=i.sup.th multipath replica of the baseband signal delayed by a time T.sub.i after the direct signal;

cos .phi..sub.1 =weighting function for the direct signal;

cos .phi..sub.i =weighting function for the i.sup.th multipath;

.phi..sub.1 =phase angle difference between the carrier of the direct signal and the oscillator reference in the synchronous demodulator; and

.phi..sub.i =phase angle difference between the carrier of the ith multipath and the oscillator reference in the synchronous demodulator.

The second signal S'Q is a signal which also contains multiple replicas, but each replica is weighted by the sine of the respective phase angle difference:

S'Q(t)=S.sub.1 (t-T.sub.1) sin .phi..sub.1 +S.sub.2 (t-T.sub.1 -T.sub.2) sin .phi..sub.2 +S.sub.1 (t-T.sub.1 -T.sub.1) sin .phi..sub.1

where S'Q(t)=quadrature output of the synchronous detector.

The two signals S'I and S'Q are processed independently and identically as shown in FIG. 2a. The correlator subsystems 104 and 104' both receive the reference signal R from PN generator 106. The signal replicas are converted to correlation signals CI.sub.i and CQ.sub.i through performance of a series of 256-point correlations between the S'I and S'Q and the binary reference signal R which represents the identical PN code used at the transmitter. The correlation signals CI.sub.i and CQ.sub.i are fed to conventional analog to digital converters 112 and 112' for conversion to digital signal bytes. A frame sync detection circuit 110 monitors the correlation magnitude .vertline.C.sub.i .vertline. by deriving a signal which is dependent on both CI.sub.i and CQ.sub.i. This function is obtained by squaring and adding the two outputs,

.vertline.C.sub.i .vertline..sup.2 =(CI.sub.i).sup.2 +(CQ.sub.i).sup.2

The magnitude .vertline.C.sub.i .vertline. is compared to a predetermined threshold level during each sample and hold cycle. A signal above the threshold provides an output signal SYNC to timing and control circuits 108. As described subsequently, this operation is required in order to synchronize the receiver to each successive data frame.

Each data frame, which comprises eight single bit words (FIG. 3) includes a synchronization or preamble word in the initial (word 1) position. Timing and control circuits 108 are arranged such that the system resynchronizes at the beginning of each data frame by doing a continuous correlation scan operation on word 1. In this operation the PN coded reference word corresponding to word 1 is continuously circulated in the correlator circuits 104 and 104' until the combined correlation output signal .vertline.C.sub.i .vertline. is observed by frame sync circuit 110 to exceed a predetermined threshold level. When this frame sync signal is detected by circuit 110 a signal SYNC is outputted to the timing and control circuits 108 and the latter are triggered into operation and are driven under control of the timing signal SCLK through a repetitive clock cycle with results in the detection of data words 2 through 8.

Correlator circuits 104 and 104' may include surface charge transistor (SCT) correlator devices of the type described by J. J. Tiemann, et al. on pages 154 and 155 of the 1974 IEEE International Solid-State Circuits Conference "Digest of Technical Papers". A similar device is also disclosed in the U.S. Pat. No. 3,801,883 issued to J. J. Tiemann and entitled "Surface Charge Signal Correlator". The SCT correlator is a multi-stage device which may be controlled to sample an analog signal such as the baseband signal S'I and to store samples of that signal in the correlator stages. Each stage is further controlled by one bit of the reference signal R to transfer ("slosh") the stored signal charge to one sensing point or another depending on the value of the binary reference bit from the signal R. The correlator circuits 104 include eight 32-stage correlator circuits connected in series so that a total of 256 correlator stages are provided. Timing and control circuits 108 drive the correlators so that 256 consecutive samples of the signal S'I are stored and are compared against the 256 bits of the reference signal R simultaneously so that the correlation output signal CI.sub.i indicates the cross-correlation value for the signals S'I and R based on a 256-point correlation therebetween. Correlator circuits 104' are identical to circuits 104 and operate on signal S'Q in an identical fashion.

Timing and control circuits 108 control the correlator circuits in accordance with a novel control sequence which loads the analog signal samples into the correlation stages in a rolling pattern that eliminates the need to shift analog signal samples between stages. The bits of the PN coded reference signal are shifted through the stages in shift register fashion but are loaded into the correlator circuits such that the last bit of each given reference word stays in alignment (occupies the same correlator stage) with the newest analog signal sample. This loading and shifting arrangement assures that when the bits of the PN coded carrier embodied in S'I and S'Q line up with the bits of the reference word R, a full 256-point correlation is realized. If the last bit of the reference word is not maintained in alignment with the newest signal sample, the best that can be achieved is something less than a 256-point correlation and the correlation signals CI.sub.i and CQ.sub.i will not represent the optimum possible correlation output.

Successive correlation outputs, after being converted to binary bytes, are stored in registers 114 and 114' whereupon they are supplied to adaptive filter networks 115, 115' each of which includes a pair of shift registers 116 and 118, a multiplier circuit 128 and a signal processing network including adder-subtractor circuits 120 and 124, scaler circuit 122 and deadband circuit 126.

In filter 115, each successive correlation output appearing in register 114 is multiplied by multiplier 128 with a smoothed correlation signal FI.sub.i applied to multiplier 128 from the output of adder-subtractor 124 through deadband circuit 126. The value of the signal FI.sub.i is determined in accordance with the following equation:

FI.sub.i =FI.sub.i-1 +d.sub.i-1 K(CI.sub.i-1 -d.sub.i-1 FI.sub.i-1) (1)

where FI.sub.i-1 represents the value of the smoothed correlation signal that was determined during the correlation performed on the preceding data word, CI.sub.i-1 represents the correlation output signal for the preceding data word and d.sub.i-1 represents the data value (+1 or -1) that was detected for the preceding data word.

Thus, when the preceding data word was detected to be a +1 the value of the smoothed correlation function is FI.sub.i =FI.sub.i-1 +K(CI.sub.i-1 -FI.sub.i-1) and if the value of the preceding data word was determined to be a -1 the smoothed correlation function is FI.sub.i =FI.sub.i-1 -K(CI.sub.i-1 +FI.sub.i-1). The correlation output as modified by the smoothed correlation function FI.sub.i is gated from the multiplier 128 by gate circuit 130 into an accumulator circuit 132.

The Q channel correlation output CQ.sub.i is processed by a circuit 115' identical to circuit 115 and the modified correlation output generated by multiplier 128' is gated by gate circuit 130' to accumulator 132. The I and Q channel outputs are combined by an adder 131 before presentation to the accumulator. A detector circuit 134 provides a data output signal on a line 138 for each data word after the modified correlation outputs for that word have been accumulated in accumulator 132. A gate circuit 134a operated by a single-shot multivibrator 136 gates the output from detector 134 to line 138 after the appropriate accumulation (integration) period for each data word. Delay circuit 137 provides a reset signal RST for restoring the accumulator to its original state in preparation for the next integration cycle.

In the above equation (1), the term K(CI.sub.i-1 -FI.sub.i-1 d.sub.i-1) is determined by the adder-subtractor 120 which receives one input from shift register 116 and another input from shift register 118. The latter stores the smoothed correlation output values calculated during detection of the preceding data word and thus supplies an input equal to FI.sub.i-1. Shift register 116 stores the correlation outputs generated during the detection of the preceding data word and thus supplies an input representing CI.sub.i-1. The value d.sub.i-1 (+1 or -1) for the preceding data word supplied on output line 138 is fed back on line 139 and sets adder-subtractor 120 to either the add state or the subtract state, depending upon the polarity of the preceding data word. Scaler circuit 122 multiplies the output from adder-subractor 120 by a predetermined scaling constant K so that it supplies at its output the term K (CI.sub.i-1 -d.sub.i-1 FI.sub.i-1).

Adder-subtractor 124 processes the latter signal by adding it to or subtracting it from the output of shift register 118. As above stated, the latter supplies a signal representing FI.sub.i-1. Adder-subtractor 124 is also controlled by the signal on line 139 representing the polarity of the last detected data word. Thus, the signal from scaler 122 is either added to or subtracted from the signal from shift register 118 and the output signal FI.sub.i represents the smoothed correlation output FI.sub.i in accordance with the above equation (1). Deadband circuit 126 passes the signal FI.sub.i on to multiplier 128 unaltered if the value of FI.sub.i exceeds a predetermined threshold. However, if the threshold is not exceeded, deadband circuit 126 supplies a 0 to multiplier 128.

As previously mentioned, the Q channel circuit 115' is identical to I-channel circuit 115 and its operation is the same as described above.

Thus, in operation, timing and control circuits 108 operate to initially load the PN reference code for word 1 into correlators 104 and 104' and to control the correlators to perform a continuous sequence of 256-point correlations between input signals S'I and S'Q and the reference code. When a desired correlation output signal .vertline.C.sub.i .vertline. is detected by frame sync circuit 110, the PN reference code for word number 2 is loaded into the correlator circuits and at a time which is determined by the time of occurrence of the initial SYNC signal, timing and control circuits 108 control the correlators to perform a series of 256-point correlations during a "sampling window." The latter defines an interval during which a high correlation match between the PN reference code and word 2 will be achieved. All correlation outputs CI.sub.i and CQ.sub.i generated during this sampling interval are processed through the adaptive filters and accumulated in accumulator 132. As correlations are performed over a sequence of sampling intervals representing several data words the adaptive filters build up the smoothed correlation functions FI.sub.i and FQ.sub.i which, operating through multipliers 128 and 128', further enhance the correlation output signals and suppress noise therefrom.

The duration of the sampling interval is set such that all atmospheric and spectral multipath components of the main signal will arrive at the receiver during the sampling interval. Multipath components will be processed by both correlator circuits and by both adaptive filters in the same manner as the main signal component such that at the end of the sampling interval accumulator 132 will contain the sum of all modified correlation outputs generated by both the main and multipath signals. The detected output signal appearing on line 138 is thus a composite of the main and multipath signal components.

The output signal at 138 is the signal to noise ratio of the weighted sum of each term of the multipath signal and an independent noise. The amplitude weighting has been done proportional to the signal strength of each component. Each component has been optiminally weighted independent of its phase delay. The output SNR ratio has a maximum positive value if a +1 (d.sub.i) has been transmitted, and has a maximum negative value (signal to RMS noise ratio) for a-1 (d.sub.i). The detection SNR is identical to the SNR of multiple coherent phase tracking receivers.

The system of the present invention is therefore capable of detecting not only main signal components but also the multipath repetitions thereof and utilizes the latter to improve the signal detection function (SNR). Fading of the multipath does not appreciably affect the detected output. Furthermore, as the characteristics of the environment change, altering the characteristics of the multipath, the adaptive filters cause the smoothed correlation function signals FI.sub.i and FQ.sub.i to change accordingly such that the processing gain of the system remains extremely high regardless of the characteristics of the environment.

DETAILED DESCRIPTION OF EMBODIMENT

Referring to FIGS. 4a and 4b, the circuit details of the correlator circuits 104 and 104', PN generator 106 and timing and control circuits 108 of FIG. 2 are hereinafter described. PN generator 106 includes a read only memory (ROM) 250 (FIG. 4b) and associated readout circuits including a 5 bit address counter 252, gate circuit 254, single-shot multivibrator circuit 256 and flip-flop 258. ROM 250 stores eight 256-bit binary reference words representing the eight PN codes associated with words 1 through 8 of each of the transmitted data frames (FIG. 3). The enlarged offset 250' shown in FIG. 4b indicates the manner in which the 256 bits of preamble word W1 are stored in memory 250. The bits of words 2 through 8 are stored in a similar fashion. As shown, the reference bits are stored in eight columns of 32 bits each. Bit R256 is the last bit in the PN code sequence and bit R1 is the first bit in the sequence.

Address counter 252 has its five output lines connected to the readout drivers of memory 252 through gate circuit 254. Each of the 32 combinations of outputs of counter 252 causes a different row of reference bits to be read out of memory 250 and to appear on output lines 251. A counter output of 00000 reads out the row of reference bits beginning with bit 256 (see offset 250') and a counter output of 11111 reads out the row of reference bits beginning with bit R225.

Address counter 252 is reset to 00000 by an output from single-shot multivibrator 256. The counter is incremented by SCLK, which is the basic system clock signal (see FIG. 9) supplied by a conventional square wave oscillator (not shown). When single-shot 256 resets counter 252, it also sets flip-flop 258 whereupon gate circuit 254 is opened. This allows the 00000 output from the counter to read out the first row of reference bits from memory 250. At the same time an AND circuit 260 responds to the all-zero output from counter 252 and produces a scan bit signal which is presented to the correlator circuits. On the next SCLK pulse, the counter 252 increments to 10000 and the second row of PN reference bits is read out of the memory. After 32 SCLK pulses, all 32 rows of reference bits have been read out of the memory. The 33rd SCLK pulse causes a carry signal to appear on counter output line 253 which resets flip-flop 258 and closes gate 254. This prevents any further readout of memory 250 until single-shot 256 is again energized.

Single-shot 256 is controlled by signals from the timing and control circuits 108 shown on the left portion of FIG. 4b. The timing and control circuits include a twenty stage cycle counter 270, a pair of decode circuits 272 and 284, a gate circuit 286 and a ROM address register 288. In addition, the timing and control circuits include control flip-flops 276, 292 and 294 as well as a single-shot 278 which is energized in response to actuation of a manual reset key 280 or by an output from decode circuit 272.

Operation of the system is initiated by actuation of manual reset key 280 whereupon single-shot 278 is energized through OR gate 282. The output from single-shot 278 resets cycle counter 270 such that the outputs therefrom are all zeros with the exception of the 8th bit position, which is set to the one state. The output from single-shot 278 also triggers single-shot 256 which initiates readout of a reference word from memory 250 as previously described. In addition, the output from single-shot 278 resets flip-flop 276 and causes flip-flop 292 to be set through OR gate 295. Also, resetting of flip-flop 276 forces address register 288 to an all-zero state, causes flip-flop 294 to set and conditions AND gate 225 in the correlator circuits (FIG. 4a).

The timing and control circuits remain in the state just described until a SYNC input is received from frame sync circuit 110. SYNC operates to set slip-flop 276. This does not occur until the correlation circuits detect a correlation match between the preamble reference word W1 and the received baseband signal S'I-S'Q. When SYNC occurs, flip-flop 276 conditions AND gate 274 such that on the next SCLK pulse cycle counter 270 starts counting. Also, setting of flip-flop 276 removes the zero hold signal from address register 288 and deconditions AND gate 225 in the correlator circuits.

When counter 270 reaches a count of 44, flip-flop 292 receives a set input through OR 295 (although as is noted from the above description flip-flop 292 is already in the set condition).

When counter 270 reaches a count of 204, gate 286 opens to transfer a count of 100 to address register 288 and at the same time the "204" output of decoder 284 causes OR 264 to energize single-shot 256 in the PN generator circuits. The latter action initiates the previously described 32-pulse memory readout operation, although this time the 256 bits of reference word W2 are read out due to the 100 count in register 288.

Thirty-three clock pulses later, after the bits of word W2 have been read out of the memory, counter 270 reaches a count of 236 and decode circuit 284 generates an output signal which resets flip-flop 292. This actuates AND gate 298 and generates a control signal A which defines the sampling interval for the correlator circuits (to be described subsequently) and permits the actuation of analog/digital converters 112 and 112' to convert the correlation output signals CI.sub.i and CQ.sub.i to digital form. Cycle counter 270 continues to increment and when it reaches a count of 257 the 0 through 7 output stages of the counter return to an all-zero state and the 8, 9 and 10 stages of the counter assume the values 0-1-0, respectively. When the 0 through 7 counter stages again reach a count of 44, flip-flop 292 is set and control signal A terminates, disabling AND gate 235 (FIG. 4a) and turning off analog-digital converter 112 and its Q channel counterpart 112'.

When the 0 through 7 stages of counter 270 again reach a count of 204, gate 286 is again opened and the count of 010 is entered into address register 288. At the same time