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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method and apparatus for detecting a
position of a substrate by detecting a mark put on the substrate, and more
particularly to method and apparatus suitable for detecting a position of
a semiconductor wafer on an exposure apparatus for manufacturing a
semiconductor device, laser repair apparatus or test apparatus.
2. Description of the Prior Art
Microminiturization of a large scale integrated circuit (LSI) pattern has
been advancing year by year, and various projection type exposure
apparatus which transfer a pattern on a mask (or reticle) onto a
semiconductor wafer with unity magnification or at a reduced scale, have
been used as circuit pattern print apparatus which meet requirements on
microminiturization and which have a high productivity.
In the manufacture of the LSI, several or more pattern layers are
sequentially formed on the wafer. If an alignment error (positional error)
between the layers is not within a predetermined range, an intended
conduction or insulation condition between the layers is not attained and
the LSI does not perform its intended function. For example, for a circuit
having a minimum line width of 1 .mu.m, only a positional error of 0.2
.mu.m at most is permitted. Accordingly, in the projection type exposure
apparatus, various high precision alignment methods have been proposed to
align a projection image of a pattern on the mask (or reticle) to a
pattern (chip) formed on the wafer.
Most of those alignment methods optically detect an alignment key mark
formed on the wafer. Accordingly, in many cases, the alignment precision
depends on the alignment mark on the wafer. The affect of the wafer
process to the alignment mark is larger in later step of the process, and
the geometry of the mark is more degraded in the later step. This means
that a photo-electric signal detected from the mark includes a distortion
due to the geometry degradation together with a high optical reflection
factor on a surface of a metalized (Al) wiring layer in the latter step of
the process of the optical alignment. As a result, the precision of
position detection of the mark is lowered and the alignment precision is
lowered. Since a higher alignment precision is required as the wafer
process proceeds, the alignment is not done in a good condition because of
the lower precision due to the degradation of the mark geometry, and a
yield of the chip is reduced.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide position detection
method and apparatus which allow high precision and high speed position
detection even for a substrate whose surface geometry is degraded during a
process.
It is another object of the present invention to provide position detection
method and apparatus in which a diffraction grating and a stepped edge are
provided on a substrate in a predetermined positional relationship, and a
position of generation of a scattered light (or normal reflection light)
from the stepped edge is determined based on a position of generation of a
diffraction light from the diffraction grating so that an edge position is
determined with a high precision from the low S/N ratio scattered light
(or normal reflection light) information.
It is other object of the present invention to provide position detection
method and apparatus which separately detect diffraction light information
and scattered light information so that an optimum detection algorithm is
applied to both signal processing based on the diffraction light
information and signal processing based on the scattered light information
.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a partial perspective view of a geometry of an alignment mark
used in the present invention,
FIG. 2 is a plan view showing a positional relationship between a chip on a
wafer and an alignment mark,
FIG. 3 is a perspective view of a projection type exposure apparatus which
uses the position detection apparatus of the present invention,
FIG. 4 is a plan view showing a positional relationship between an image
field of a projection lens and a spot light,
FIG. 5 shows a photo-electric detection unit,
FIG. 6 is a plan view of a spatial filter for detecting a scattered light,
FIG. 7 is a plan view of a spatial filter for detecting a diffraction
light,
FIG. 8 is a block diagram of a signal processing circuit,
FIG. 9 is a flow chart showing a position detection procedure,
FIG. 10 is a plan view showing a positional relationship between an
alignment mark and a spot light,
FIGS. 11a-11b shows an intensity distribution of the diffraction light and
an intensity distribution of the scattered light,
FIG. 12 shows a geometry of the alignment mark affected by the process and
an intensity distribution of the diffraction light,
FIGS. 13a-13b is a plan view illustrating the affect to the diffraction
grating pattern by the process,
FIGS. 14a-14b show waveforms for illustrating gain control of
photo-electric signals SA and SB of the diffraction light information,
FIG. 15 is a block diagram of another embodiment of the signal processing
circuit,
FIG. 16 shows another embodiment of the scattered light information
receiving unit,
FIGS. 17a and 17b are plan views of other embodiments of photo-sensing
elements which sense the diffraction light information and the scattered
light information,
FIG. 18 shows a gain control circuit in a phase synchronization detection
system signal processing circuit,
FIG. 19 is a plan view showing a geometry of a spatial filter for detecting
a normal reflection light, and
FIG. 20 is a plan view showing other geometries of the alignment mark and
the spot light.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is an enlarged perspective view, partially in section, showing a
geometry of an alignment mark on a wafer in accordance with an embodiment
of the present invention. The mark of the present invention has a pair of
diffraction grating marks Ma and Mb formed on the wafer.
The marks Ma and Mb have small rectangular patterns (grating elements) Pa
and Pb, respectively, arranged at a constant pitch in a y-direction of an
x-y coordinate to allow x-direction position detection. The rectangular
patterns Pa of the mark Ma are projecting patterns on the surface of the
wafer W and each rectangular pattern Pa has a y-direction width of d.sub.1
and an x-direction width of d.sub.2. A spacing between the patterns Pa is
d.sub.3. The widths d.sub.1 and d.sub.2 and the spacing d.sub.3 are
selected such that a diffraction light is generated efficiently by the
irradiation of the alignment light beam. On the other hand, a projecting
rectangular area (land) Pc is formed on the surface of the wafer W
adjacently to the mark Ma. The rectangular area Pc has stepped edges
E.sub.1 and E.sub.2 which continuously extend along the y-direction. In
the present embodiment, a height of the rectangular area Pc is equal to a
height of the rectangular patterns Pa of the mark Ma. The mark Mb
extending in the y-direction is formed in the rectangular area Pc. The
mark Mb has small rectangular patterns Pb which have the same shape and
dimension as those of the rectangular patterns Pa of the mark Ma but the
rectangular patterns Pb are recessed. The recessed grating patterns of the
mark Mb also generate a diffraction light when they are irradiated by the
alignment light beam.
In the present embodiment, a distance between a center axis of the mark Ma
along the x-direction and a center axis of the mark Mb along the
x-direction is l.sub.0, a distance between the center axis of the mark Ma
and the stepped edge E.sub.2 is l.sub.1, and distances between the center
axis of the mark Mb and the stepped edges E.sub.1 and E.sub.2 are l.sub.3
and l.sub.2, respectively.
The marks Ma and Mb and the rectangular area Pc (which are collectively
called an alignment mark) are formed in the course of exposure process of
a first layer to the wafer W. FIG. 2 is a plan view showing the
arrangement of the alignment mark formed on the wafer W. In the present
embodiment, the first layer is exposed by a reduction projection type
exposure apparatus (stepper) and the alignment marks in the x-direction
and y-direction are formed for each chip area CP on the wafer W. A reticle
for the first layer has a pattern for forming the mark shown in FIG. 1.
The chip area CP is arranged in matrix on the wafer W and corresponds to
one exposure field (shot) of the reduction projection type exposure
apparatus. The chip area CP may include one circuit pattern or a plurality
of circuit patterns of the same design (multi-die). When an x-y coordinate
is defined with a center O of the chip area CP being an origin, the
alignment mark used for the x-direction position detection is positioned
on the y-axis and the alignment mark used for the y-direction position
detection is positioned on the x-axis. The x-direction alignment mark
comprises marks Max, Mbx and a rectangular area Pcx like that shown in
FIG. 1, and the y-direction alignment mark similarly comprises marks May
and Mby and a rectangular area Pcy extending in the x-direction. In the
present embodiment, in order to simplify the description, it is assumed
that the y-axis passes through a point which is spaced by a distance
x.sub.1 from both of the marks Max and Mby (x.sub.1 =l.sub.0 /2), and the
x-axis passes through a point which is spaced by a distance y.sub.1 from
both of the marks May and Mby (y.sub.1 =l.sub.0 /2). By photo-electrically
detecting those two alignment marks and measuring the positions of the
marks, two-dimensional alignment of projection images of the second and
subsequent circuit patterns and the chip area CP. In the present
embodiment, the pair of diffraction grating marks Ma and Mb having the
same shape and dimension, one projecting and the other being recessed, are
formed on the wafer W in order to suppress reduction of the detection
precision due to a waveform distortion of the photo-electric signal by the
deformation or degradation of the mark geometry as the wafer process
proceeds or by the uneven thickness of applied photoresist
(photo-sensitive material). The projecting mark and the recessed mark,
even if their shapes and the dimensions are equal, are differently
affected by the process and the resist. Accordingly, even if one of the
projecting and recessed marks is significantly deformed, there is a high
possibility that the geometry of the other mark is retained. Thus, by
selecting the less deformed mark, the reduction of the detection precision
can be suppressed.
FIG. 3 is a perspective view of a reduction projection type exposure
apparatus suitable for incorporation in the position detection apparatus
of the present invention. A reticle R which is an original plate to be
projected is mounted on the apparatus such that a projection center
thereof passes through an optical axis AX of a projection lens 1. The
projection lens 1 projects a circuit pattern image drawn on the reticle R
onto a wafer W at a reduction factor of 1/5 or 1/10. A wafer holder 2
vacuum-chucks the wafer W and is finely movable to a stage 3 which is
two-dimensionally moved in the x-direction and y-direction. The
x-direction movement of the stage 3 is done by a motor 5 and the
y-direction movement is done by a motor 6. A reflection mirror 7 having a
reflection plane extending in the y-direction and a reflection mirror 8
having a reflection plane extending in the x-direction are fixed to two
orthogonal sides of the stage 3. A laser interferometer 9 projects a laser
beam to the reflection mirror 8 to detect a y-direction position (or
displacement) of the stage 3, and the laser interferometer 10 projects a
laser beam to the reflection mirror 7 to detect an x-direction position
(or displacement) of the stage 3.
The present apparatus has a laser step alignment (LSA) optical system for
detecting a mark on the wafer W through the projection lens. A laser beam
LB emitted from a laser beam source (not shown) and passed through an
expander and a cylindrical lens (not shown) has a wavelength which is not
sensed by a photoresist, and it is divided into two light beams by a beam
splitter 30. One of the laser beams is reflected by a mirror 31, passes
through a beam splitter 32 and focused by a focusing lens 33 such that a
cross-section thereof is of belt shape. Then, the laser beam is directed
to a first mirror 34 arranged between the reticle R and the projection
lens 1 so that it does not interrupt a projection path of the circuit
pattern. The first mirror 34 reflects the laser beam toward the reticle R.
The laser beam is directed to a mirror 35 which is arranged below the
reticle R and a reflection plane parallel to the surface of the reticle R
and, reflected toward a center of an incident pupil of the projection lens
1. The laser beam from the mirror 35 is focused by the projection lens 1
onto the wafer W as a belt-shaped spot light (strictly describing, an
elliptical-shaped spot light of striped pattern of several lens to several
ten .mu.ms.) LYS extending in the x-direction. The spot light LYS scans
the diffraction grating marks May and Mby extending on the x-direction on
the wafer W or the stepped edges E.sub.1 and E.sub.2 of the rectangular
area Pcy in the y-direction to detect the position of the y-direction
alignment mark. As the spot light LSY illuminates the y-direction
alignment mark, a diffraction light and a scattered light (reflection
light) are generated from the alignment mark. The light information passes
through the lens 1, mirror 35, mirror 34, focusing lens 33 and beam
splitter 32, is reflected by the beam splitter 32 and directed to a
photo-electric detector 38 through a lens 36 and a mirror 37. The
photo-electric detector 38 produces photo-electric signals which represent
a light intensity of the incident diffraction light and a light intensity
of the incident scattered light, respectively. The mirror 31, beam
splitter 32, focusing lens 33, mirrors 34 and 35, lens 36, mirror 37 and
photo-electric detector 38 form a through-the-lens type alignment optical
system (Y-LSA system).
On the other hand, the other laser beam split by the beam splitter 30 is
directed to a through-the-lens type alignment optical system (X-LSA
system) which detects the position of the X-direction alignment mark on
the wafer W. The X-LSA system comprises mirror 41, beam splitter 42,
focusing lens 43, mirrors 44 and 45, lens 46, mirror 47 and photo-electric
detector 48, like the Y-LSA system and focuses a belt-shaped
(stripe-shaped) spot light LXS extending in the y-direction on the wafer
W.
A main control unit 50 receives the photo-electric signals from the
photo-electric detectors 38 and 48 and the position information from the
laser interferometers 9 and 10 to process the information for position
detection and positioning and issue commands to drive the motors 5 and 6.
The main control unit 50 has a processor such as a microcomputer or
minicomputer and stores therein design position information of chip areas
CP formed on the wafer (chip arrangement coordinates on the wafer W) and
design position and dimension of the alignment mark.
FIG. 4 is a plan view showing the arrangement of the two spot lights LYS
and LXS on the wafer W. A circle area shows a view field (image field) if
of the projection lens 1. When the reticle R is precisely positioned to
the apparatus, the projection image of the circuit pattern of the reticle
R is a rectangular area Pr through a center of which the optical axis AX
passes. The area Pr may be as large as to internally contact to the image
field if. If the coordinate axes are defined such that the optical axis AX
passes through the origin point of the x-y movement coordinate (orthogonal
coordinate) of the stage 3, the spot light LXS is located at a position on
the y-axis spaced by a distance YP from the optical axis AX, and the spot
light LYS is located at a point on the x-axis spaced by a distance XP from
the optical axis AX.
FIG. 5 shows an embodiment of the photo-electric detectors 38 and 48. Since
both photo-electric detectors are identical in construction, only the
photo-electric detector 48 is shown. The light information from the
x-direction alignment mark reflected by a mirror 47 includes diffraction
lights .+-.D (.+-.1-order lights, .+-.2-order lights, .+-.3-order lights,
etc.) generated by the marks Max and Mbx, diffraction light D.sub.0 from
the stepped edges E.sub.1 and E.sub.2 or steps of the marks Max and Mbx
parallel to the edges E.sub.1 and E.sub.2, and normal reflection light.
The light information is divided into two by a beam splitter 60, and one
of the light information is directed to a spatial filter 61 arranged in
conjugation with an incident pupil of the projection lens 1 so that only a
scattered light D.sub.0 is extracted from an aperture 61a and focused to a
plane of a photo-electric element 63 through a condenser lens 62. The
other light information from the beam splitter 60 is directed to a spatial
filter 64 arranged in conjugation with the incident pupil of the
projection lens 1 and only the diffraction lights .+-.D from the marks Max
and Mby are extracted from apertures 64a and 64b. The diffraction lights
.+-.D are directed to a prism-like glass block 65 having two reflection
surfaces 65a and 65b. On the reflection surface 65a, the diffraction light
+D (+1-order light, +2-order light, +3-order light) is reflected and it is
focused to a plane of a photo-electric element 67 through a condensing
lens 66. On the other hand, on the reflection surface 65b, the diffraction
light -D (-1-order light, -2-order light, -3-order light) is reflected and
it is focused to a plane of a photo-electric element 69 through a
condensing lens 68.
FIGS. 6 and 7 are plan views showing the shapes of the spatial filters 61
and 64, respectively. In FIG. 6, a light beam distribution LX' on the
incident pupil of the normal reflection light of the spot light LXS is
shown at the center of the spatial filter 61. The spatial filter 61 is
conjugate with the incident pupil of the projection lens 1, and the light
beam distribution LX' extends orthogonally to the spot light LXS on the
spatial filter 61 because the light transmission system for the laser beam
includes the cylindrical lens. The spatial filter 61 has apertures 61a and
61b which block the normal reflection light and transmit the scattered
light D.sub.0 generated when the spot light LXS is illuminated to the
stepped edges E.sub.1 and E.sub.2. The apertures 61a and 61b are arranged
symmetrically around a longitudinal center axis of the spot light LXS,
that is, on the left and right of the light beam distribution LX'. On the
other hand, the spatial filter 64 shown in FIG. 7 is also arranged in
conjugation with the incident pupil of the projection lens 1 and the light
beam distribution LX' of the normal reflection light from the wafer W of
the spot light LXS extends orthogonally to the spot light LXS on the
spatial filter 64. The spatial filter 64 has apertures 64a and 64b which
block the normal reflection light and transmit the diffraction lights
.+-.D from the marks Ma and Mb. The aperture 64a is designed to transmit
the +1-order light (+D1), +2-order light (+D2) and +3-order light (+D3)
from the marks Ma and Mb, and the aperture 64b is designed to transmit the
-1-order light (-D1), -2-order light (-D2) and -3-order light (-D3). As
the diffraction lights +D are divided into the plus order light and the
minus order light and sensed by the different photo-electric elements 67
and 69, photo-electric signals SA and SB from the photo-electric elements
67 and 69 can be separately processed so that the reduction of the
position detection precision due to the change or degradation of the
diffraction grating pattern can be suppressed.
FIG. 8 shows an embodiment of a processing circuit which receives the
photo-electric signals SA, SB and SC from the photo-electric elements 67,
69 and 63. The processing circuit is provided in the main control unit 50
and it cooperates with a processor such as a microcomputer or minicomputer
to detect the positions of the marks Ma and Mb and the stepped edges
E.sub.1 and E.sub.2. In FIG. 8, the photo-electric signal SA is amplified
by a preamplifier 80 having a predetermined amplification factor and an
output thereof is applied to a gain control amplifier (AGC circuit) 81,
which adjusts a level of the input signal by a preset gain to produce a
signal SA'. On the other hand, the photo-electric signal SB is amplified
and adjusted by similar preamplifier 82 and AGC circuit 83, which produces
a signal SB'. A summing circuit 84 produces a signal SD which is an analog
sum of the two signals SA' and SB'. An analog-digital converter (ADC) 85
samples the signal SD and converts it to a digital signal representing the
magnitude (level) of the analog signal. A random access memory circuit
(RAM) 86 stores the digital signal sampled by the ADC 85 at a designated
address. The sampling by the ADC 85 and the addressing of the RAM 86 are
done by a pulse signal SP from the laser interferometer 10. The pulse
signal SP is a pulse train which is generated one pulse each time the
stage 3 is moved by a unit distance (for example, 0.02 .mu.m) in the
x-direction. In response to each pulse, the ADC 85 samples once and the
address of the RAM 86 is incremented (or decremented) by one.
The photo-electric signal SC is amplified by preamplifier 87 and AGC
circuit 88, and a signal SC' therefrom is sampled by an ADC 89 and stored
in a RAM 90 in the sequence of address. The sampling by the ADC 89 and the
addressing of the RAM 90 are done in response to the pulse of the pulse
signal SP from the laser interferometer 10. The processor (CPU) such as
the microcomputer or minicomputer receives the digital information from
the RAM 86 and the RAM 90 and the x-direction position information of the
stage 3 (resolution of which is determined by the unit distance of
movement) read by the laser interferometer 10 and processes them by a
software to detect the positions of the marks Max and Mbx and the stepped
edges E.sub.1 and E.sub.2. In the present embodiment, the projection image
of the reticle R is finally aligned to the chip CP on the wafer W. Thus,
the CPU 100 controls the positioning motors 5 and 6 for the stage 3 in
accordance with the detected mark position information and edge position
information. The CPU 100 also issues commands to individually change the
gains of the AGC circuits 81, 83 and 88.
In the RAM 86, the x-direction intensity distribution (photo-electric
distribution) of the diffraction lights from the marks Max and Mbx is
stored at corresponding locations, and in the RAM 90, the x-direction
intensity distribution (photo-electric waveform) of the scattered lights
from the stepped edges E.sub.1 and E.sub.2 or the steps of the marks Max
and Mbx which are parallel to the stepped edges E.sub.1 and E.sub.2 is
stored at corresponding locations. The AGC circuit 88 need not be very
precise but it may be an amplifier having two or three gain ranges because
the intensity of the scattered light may significantly change by an affect
of the resist on the wafer W or an underlying material. On the other hand,
the AGC circuits 81 and 83 are preferably precise variable gain amplifiers
in order to compensate for deformation or degradation of the diffraction
grating pattern (marks Ma and Mb) on the wafer W. For example, when the
width of the spot light LXS is equal to the width d.sub.2 of the marks Max
and Mbx and the marks Max and Mbx and the spot light LXS are relatively
scanned in the x-direction, the waveforms of the photo-electric signals SA
and SB are Gauss waveforms. If the diffraction grating pattern has no
deformation or degradation, the sizes of the photo-electric signals SA and
SB and the x-direction positions are identical. However, the sizes of the
Gauss waveforms of the photo-electric signals SA and SB differ from each
other depending on the degree of deformation of the diffraction grating
pattern and the x-direction positions also slightly change from each other
(positional shift of the photo-electric signals SA and SB). The
distortions of the Gauss waveforms of the photo-electric signals may also
differ from each other. When the marks Ma and Mb are straight grating
patterns as they are in the present embodiment or oblique grating patterns
comprising 45.degree. fine line elements as disclosed in U.S. Pat. No.
4,423,959, the difference in the sizes of the Gauss waveforms of the
photo-electric signals SA and SB leads to the reduction of the detection
precision. In the present embodiment, when the sizes of the waveforms of
the photo-electric signals SA and SB are different, the gains of the AGC
circuits 81 and 83 are controlled to equalize the sizes of the waveforms
of the signals SA' and SB' and they are summed in the summing circuit 84.
The operation of the present embodiment is explained with reference to a
flow chart of FIG. 9. It is assumed that mechanical prealignment and
global alignment of the wafer W have been completed and alignment for each
chip CP (step alignment) is to be carried out.
The CPU 100 first positions the stage 3 so that the x-direction alignment
mark of the chip CP to be exposed and the spot light LXS are arranged in
parallel (step 200). This is shown in FIG. 10. The spot light LXS is
spaced from the mark Max on the left side thereof. The positioning in this
step is generally attained with an error of less than 1 .mu.m although it
depends on the global alignment precision. The CPU 100 reads the current
x-direction position of the stage 3 from the laser interferometer 10 and
stores it as a start of scan point Cxo, and instructs the RAM's 86 and 90
to write digital values starting from the address O. The x-direction
alignment mark shown in FIG. 10 is same as that shown in FIG. 1. It is
assumed that the distances l.sub.1 and l.sub.2 are equal to the spacing
x.sub.1. Accordingly, as seen from the mark arrangement shown in FIG. 2,
an extended line of the stepped edge E.sub.2 passes through the center of
the chip CP.
The CPU 100 then starts the relative scan of the spot light LXS and the
x-direction alignment mark (step 201). This is done by moving the stage 3
in the x-direction relative to the spot light LXS. This is called a stage
scan. The stage scan is carried out over a distance sufficient for the
spot light LXS to cross the mark Max, stepped edge E.sub.2, mark Mbx and
stepped edge E.sub.1. The distance is determined by a sum of l.sub.1,
l.sub.2 and l.sub.3. For example, it is 100 .mu.m. During the stage scan,
the ADC's 85 and 89 sample the signals SD and SC', respectively, and the
results are stored in the RAM's 86 and 90 in the order of addresses. When
the distance of the stage scan is 100 .mu.m and the sampling interval
(increment) is 0.02 .mu.m, the number of sampling points is 5000
(addresses 0-5000). At the end of the stage scan, a distribution waveform
as shown in FIG. 11a has been stored in the RAM 86, and a distribution
waveform as shown in FIG. 11b has been stored in the RAM 90. In FIGS. 11a
and 11b, the abscissas represent the x-positions which are uniquely
related to the addresses of the RAM's 86 and 90. The ordinates represent
the diffraction light intensity I (level of the signal SD) and the
scattering light intensity J (level of the signal SC'). As seen from FIG.
11a, at a point C.sub.1 where the spot light LXS coincides with the mark
Max, the diffraction light intensity I is peak (peak point of the Gauss
waveform), and at a point C.sub.2 where the spot light LXS coincides with
the mark Mbx, the diffraction light intensity I is peak. The marks Max and
Mbx are diffraction gratings in order to enhance a recognition factor for
any irregular pattern on the wafer W. If the degradation of the mark
geometry is small, an S/N ratio of the peak waveform is fairly high.
The CPU 100 then reads the distribution waveform stored in the RAM 86 to
detect the points C.sub.1 and C.sub.2 (step 202). It may be detected by
(a) binarizing the distribution waveform shown in FIG. 11a by a
predetermined slice level and detecting the points C.sub.1 and C.sub.2 by
mid-points of the widths of the peak waveforms, (b) primarily
differentiating the distribution waveform and detecting the points C.sub.1
and C.sub.2 by zero-crossing points on the differentiated waveform, or (c)
integrating the peak waveforms in the distribution waveform and detecting
the points C.sub.1 and C.sub.2 by centers of gravity of the peak
waveforms. Any other detection method may be used.
The CPU 100 then determines if the marks Max and Mbx are on a layer
deformed or degraded by the process (step 203). This is done by storing in
the CPU what an operator experimentarily knew. For second and third
layers, it may be possible that the deformation of the marks by the
process is little and the deformation of only the mark Max (convex
pattern) is prominent as the process proceeds and in the last layer, the
mark Max is significantly degraded and the mark Mbx (concave pattern) is
also prominent. In this case, information is stored in the CPU 100 such
that both or one of the marks Max and Mbx are used for the second and
third layers, only the mark Mbx is used for the subsequent layer, and the
stepped edges E.sub.1 and E.sub.2 in addition to the mark Mbx are used for
the last layer together with the scattered light information. If the
deformation or degradation of the marks Max and Mbx is not predictable,
the conditions of the marks may be observed by a TV camera through the
alignment optical system shown in FIG. 3, and an operator instructs an
appropriate processing to the CPU 100.
In the step 203, if it is determined that the influence by the process is
small and the distortion of the diffraction light signal from the mark Max
or Mbx is very small, it is determined whether both or one of the marks
Max and Mbx are to be used (step 204). Since the diffraction light
photo-electric signal has a high S/N ratio, a high position detection
precision is attained if the deformation or degradation is not included.
If the both marks Max and Mbx are not deformed, the two marks are used to
detect the x-direction position Xe of the alignment mark (step 205). When
the spot light LXS is positioned at the mid-point of the marks Max and
Mbx, the chip center is aligned to the optical axis AX in the x-direction.
Accordingly, the CPU 100 calculates the position Xe in the step 205 in
accordance with a formula
##EQU1##
If the mark Max has a significant deformation but the mark Mbx has no
prominent deformation (or vice versa), only the mark Mbx having little
deformation is used to detect the position Xe (step 206). Since the mark
Mbx is spaced from a line which is parallel to the y-axis and passes
through the chip center by +x.sub.1 (l.sub.2) in the x-direction, the
position Xe is calculated in accordance with a formula
Xe=C.sub.2 -x.sub.1
If it is determined in the step 203 to use the scattered light information
as well, the CPU 100 detects positions C.sub.5 and C.sub.8 corresponding
to the peak points created by the edges E.sub.1 and E.sub.2 in the
distribution waveform of the scattered light intensity (step 207) based on
the positions C.sub.1 and C.sub.2 of the marks Max and Mby determined from
the distribution waveform of the diffraction light intensity and design
value for the distances from the marks Max and Mbx to the stepped edges
E.sub.1 and E.sub.2, respectively. As shown in Fig. llB, the scattered
light is always generated so long as any unevenness or step exists on the
wafer W.
In other words, a sensitivity to detect the step on the wafer W is high.
The peak waveforms corresponding to the marks Max and Mbx at the positions
C.sub.3 and C.sub.4 and the positions C.sub.6 and C.sub.7, respectively,
are also obtained by the scattered light from the stepped edges of the
marks Max and Mbx extending in the y-direction. If the surface of the
wafer W is rough, small peak waveforms are generated. If the influence of
the process is so large that the marks Max and Mbx are deformed or
degraded, the distribution waveform of the scattered light intensity J
does not have a high S/N ratio as shown in FIG. 11b and the peak levels
are generally low and many noise peaks appear because the intensity of the
scattered light signal greatly depends on the inclination of the slope of
the stepped edge since, in the present embodiment, the scattered light
passing through the vicinity of the normal reflection light beam from the
stepped edge is detected on an incident pupil plane. As a result, if the
inclination of the slope changes by the influence of the process, the peak
waveforms by the stepped edges E.sub.1 and E.sub.2 are lowered and may be
hidden by the noise peak waveforms. Such scattered light information
highly reflects the unevenness on the surface of the wafer W, and it is
very difficult to detect the positions C.sub.5 and C.sub.8 of the stepped
edges E.sub.1 and E.sub.2 on the surface of the wafer W even if hardware
and software are fully utilized.
In the present embodiment, in the step 207, the CPU 100 calculates design
positions of the stepped edges E.sub.1 and E.sub.2 for the positions
C.sub.1 and C.sub.2 of the mark Max or Mbx. For example, the stepped edge
E.sub.2 is to be located near the position (C.sub.1 +l.sub.1) or (C.sub.2
-l.sub.2), and the stepped edge E.sub.1 is to be located near the position
(C.sub.2 +l.sub.3) or (C.sub.1 +l.sub.1 +l.sub.2 +l.sub.3). For the sake
of simplicity, the position (C.sub.2 -l.sub.2) is used for the edge
E.sub.2 and the position (C.sub.2 +l.sub.3) is used for the edge E.sub.1.
The CPU 100 examines the distribution waveform of the scattered light
intensity shown in FIG. 11b for a small section .+-..DELTA.x around the
calculated position. If any peak exists in the small section .+-..DELTA.x,
it must be generated by the edges E.sub.1 and E.sub.2 and the peak point
is detected as the positions C.sub.5 and C.sub.8 of the edges E.sub.1 and
E.sub.2. By limiting (gating) the search range of the distribution
waveform of the scattered light information by using the positions C.sub.1
and C.sub.2 detected in accordance with the diffraction light information,
the positions of the edges E.sub.1 and E.sub.2 can be precisely detected
at a high speed even for a low S/N ratio scattered light information. The
small section .+-..DELTA.x is preferably close to the x-direction width of
the spot light LXS.
The CPU 100 calculates an x-direction center position Xg of a rectangular
pattern Pcx based on the detected positions C.sub.5 and C.sub.8 in
accordance with a formula
##EQU2##
If the distance l.sub.3 between the stepped edge E.sub.1 and the mark Mbx
is equal to the distance l.sub.2, the position Xg is also the position
C.sub.2 of the mark Mbx. However, if the deformation or degradation of the
mark Mbx is remarkable and the peaks on the distribution waveform of the
diffraction light intensity are small and include much distortions, the
position C.sub.2 does not necessarily coincide to the center of the mark
Mbx. However, the position Xg detected by the method of determining the
center of the stepped edges E.sub.1 and E.sub.2 well coincide with the
center of the mark Mbx because the spot light LXS is elongated and the
continuous linear stepped edges E.sub.1 and E.sub.2 are not significantly
deformed by the process. This is explained with reference to FIG. 12. It
is assumed that small rectangular patterns Pa and Pb of the marks Max and
Mby have been deformed by the influence of the process and the stepped
edges E.sub.1 and E.sub.2 of the rectangular pattern Pcx have been
deformed roughly or ruggedly. It is also assumed that the stepped edges
E.sub.1 and E.sub.2 have been thinned by a small amount .DELTA..alpha.
from its inherent position. Such a phenomenon is often seen in the wafer
process and not a special one. In this case, the peak waveforms for the
marks Max and Mbx on the distribution waveform of the diffraction light
intensity I have small amplitudes and include distortions. As a result,
the positions of the marks Max and Mbx detected are shifted by small
amounts .DELTA..beta. and .DELTA..beta.' from the design positions. On the
other hand, for the edges E.sub.1 and E.sub.2, shape of edges are rough or
rugged but that microscopic roughness or ruggedness are averaged because
the spot | | |
