A DRAM controller comprises an address output controller for transferring an address-designating signal to a dynamic RAM, a data output controller for transferring data to be written into and read-out from a memory region of the dynamic RAM which is designated by the address-designating signal, and a control circuit responsive to a mode-designating signal for generating various control signals corresponding to an access mode of the dynamic RAM designated by the mode-designating signal and for supplying control signals to the dynamic RAM, address output controller, and data output controller in a predetermined sequence. In the DRAM controller, the control circuit includes a signal-generating unit for generating control signals in a specific access mode which requires an access time longer than a machine cycle of a processor for generating the address-designating signal, the data to be written, and the mode-designating signal, the signal-generating means delaying generation control signals every time designation of the specific access mode by the mode-designating signal is repeated.

A pseudo static RAM includes an array of dynamic memory cells and peripheral circuits such as precharge transistors, a row decoder and sense amplifiers. Address change detecting circuits detect address signal change. A pulse generator supplies a pulse signal to a timing generator and a busy signal generator in response to the address signal change. The timing generator generates various timing signals for driving the peripheral circuits. When a subsequent address signal change is detected during operation of a dynamic RAM, a flag circuit generates a flag signal in response to a subsequent pulse signal from the pulse generator and a busy signal from the busy signal generator. Thus, the signal commanding such subsequent operation of the pseudo static RAM is stored in the form of a flag signal until the first operation is completed. Upon completion of first operation of the dynamic RAM, subsequent operation is started on the basis of the flag signal.

A delay circuit that generates an output signal responsive to an input signal after a delay corresponding to a reference voltage that is insensitive to the power supply voltage. The output signal switches between ground and the power supply voltage (V.sub.CC). The delay circuit is formed by a timer circuit and a level translator circuit. The delay circuit provides an output signal having a delay of a fixed time period regardless of fluctuations or changes in the supply voltage. The level translator circuit provides an output signal with the aforementioned delay that has a magnitude of either the power supply voltage or ground. The timer circuit includes a capacitor that is charged and discharged through respective transistors to provide the delay. The level translator circuit includes transistors that switch the output signal between the supply voltage and ground.

A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.