In order to guarantee the instruction execution sequence in a pipeline control data processing system, the present overlap detector device detects whether or not the operands overlap each other in access width units by comparing the store address specified by a store instruction with the fetch address contained in a fetch instruction following the store instruction. Moreover, the overlap detector device detects whether or not an overlap occurs in an area of the access width based on the store mark, the address in the access width unit stored in the fetch address, and the fetch data length. The overlap detector device detects the presence or absence of an overlap according to the results of operations for detecting these two overlap conditions.
An apparatus and method for controlling memory requests in an information processor is capable of generating an effective address for a first operand and a second operand, both of which are part of an instruction used to transfer data from a first memory location to a second memory location. The first operand indicates the first memory location and the second operand indicates the second memory location. By changing, in response to address overlap of the first and second operands, control of requests for memory accessing by changing the read address of a control memory, useless memory accessing is avoided resulting in faster processing.
One aspect of the invention relates to a super scalar processor having a memory which as addressable with respect to the combination of a page address and a page offset address, and provides a method for detecting an overlap condition between a present instruction and a previously executed instruction, the previously executed instruction being executed prior to execution of the present instruction. In one embodiment, the method comprises the steps of dividing the present instruction into a plurality of aligned memory accesses; determining the page offset for at least one of the aligned accesses; and comparing the page offset and byte count for the present instruction to a page offset and byte count for the previously executed instruction.
An access hazard detection technique in a pipelined cache controller sustains high throughput in a frequently accessed cache but without the cost normally associated with such access hazard detection. If a previous request (request in the pipeline stages other than the first stage) has already resulted in a cache hit, and it matches the new request in both the Congruence Class Index and the Set Index fields and if the new request is also a hit, the address collision logic will signal a positive detection. This scheme makes use of the fact that (1) the hit condition, (2) the identical Congruence Class Index, and (3) the Set Index of two requests are sufficient to determine that they are referencing the same cache content. Implementation of this scheme results in a significant hardware saving and a significant performance boost.
A data transfer control unit comprises a first address register, a second address register and a control circuit. The first address register stores a first final address value of a memory area of a memory into which data is to be transferred. The second address register stores a second final address value of data which has already been transferred to the memory area of the memory. The control circuit compares the first final address value and a second final address value with an address value of data access by a CPU in order to generate a memory indication signal indicative of whether the address value of data accessed by the CPU belongs to the addresses of the data which has already been stored or has not yet been stored. The control circuit further prohibits a data transfer from the memory area to the CPU only when the address value of the data accessed by the CPU belongs to the addresses of the data which have not yet been stored in the memory.
Bubble compression in a pipelined central processing unit (CPU) of a computer system is provided. A bubble represents a stage in the pipeline that cannot perform any useful work due to the lack of data from an earlier pipeline stage. When a particular pipeline stage has stalled, the CPU instructions that have already passed through the stage continue to move ahead and leave behind vacant stages or bubbles. If a bubble is introduced into a pipeline and the pipeline subsequently stalls, the disclosed CPU takes advantage of this stalled condition to compress the previously introduced bubble.
