A test pattern generation device for producing test pattern signals for testing a preselected digital circuit includes a dominant pattern signal generator and a subservient pattern signal generator. When a first dominant pattern signal (0,0,0,0,0) is generated, five subservient pattern signals (1,0,0,0,0), (0,1,0,0,0), (0,0,1,0,0), (0,0,0,1,0) and (0,0,0,0,1) are generated, each being unit Hamming distance from the dominant pattern signal. The subservient pattern signals are sequentially applied to a simulator carrying a hypothetical digital circuit for producing a controllability cost CCO.sub.f and a continuous cyclic logic value CV.sub.f at a preselected line G.sub.f in the digital circuit for each subservient pattern signal. A cost generator produces an evaluation cost CT.sub.f by the use of the controllability cost CCO.sub.f and the continuous cyclic logic value CV.sub.f for each subservient pattern signal. A selector selects from the set of subservient pattern signals a subservient pattern signal that produced a minimum evaluation cost CT.sub.f, test pattern memory stores the selected subservient pattern signal as one test pattern and assigns the selected subservient pattern signal as a next dominant pattern signal in a next cycle operation.

A method for online editing of compressed digital test vectors in an automated circuit test system, without requiring re-compilation of the test program source code. A method is provided for online editing of vectors compressed in both "indirect" and "keep/toggle (K/T)" compression formats. The test system environment within which the method operates comprises a computer and associated random access memory. The method can be summarized as follows: First, a new vector is created in random access memory (RAM) by storing a copy of the target vector to be modified. Next, pointers in RAM are adjusted to point to the new vector. Then, in order to compensate for K/T compression, the vector following the target vector must be examined to determine whether it requires modification, because of a "ripple effect" caused by modification to the previous vector. If the following vector requires modification, then a copy of the vector must also be created in RAM. Pointers in RAM are also adjusted to point to the copied following vector. Finally, the target vector is modified per user input, and the copied following vector, if created, is modified to compensate for the effect(s) of K/T compression.

The present invention is a method for operating a data processing system to generate a sequence of test states containing a predetermined set of states and/or transitions for use in testing an integrated circuit or the like. The method minimizes the number of additional states and/or transitions contained in the test sequence while preserving any constraints on the sequence of transitions that may be applied to the circuit to be tested. The present invention operates by defining a graph containing the predetermined set of states and/or transitions. The states are the vertices of the graph and the transitions are edges of the graph. The graph is then augmented if needed with additional states and/or transitions. The additional states and/or transitions assure the existence of an Eulerian Path through the graph. The additional states assure that the graph is connected, and that each vertex in the graph, with the possible exception of two vertices, has the same number of inbound and outgoing transitions. The Eulerian Path is then traced to provide a sequence of states that includes the input list of states and/or transitions.

An apparatus for providing data to an I/O bus at the maximum I/O bus bandwidth comprises an exerciser unit coupled to the I/O device. The exerciser unit includes DMA circuitry for providing a constant stream of transactions to the I/O bus. Each transaction provides a plurality of data quadwords to the I/O bus which are parity protected. The exerciser unit includes a memory device for storing data to be provided for each transaction, and a parity circuit for calculating and providing parity for the data stored in the memory. The exerciser unit further includes a data generation device for providing both data having predictable parity and the parity to the bus for each bus cycle while bypassing the parity generation logic to provide data at maximum bandwidth. The data generation device provides a sequence of different data bytes using a modified Gray-code algorithm, which facilitates parity generation for each byte in the sequence of bytes.

Timing-signal delay equipment which provides an adjustable delay time, equal to a multiple of a predetermined time unit, to an input signal pulse is used as a timing source required in a circuit tester of LSIs (semiconductor large-scale integrated circuits). The timing-signal delay equipment has a plurality of delay elements (D.sub.ij 's) with weighted delay times arranged in a matrix form; a selector (S) coupled with the matrix for selecting one of the delay elements for each column of the matrix, wherein the selected delay elements are connected in series; and an arithmetic control circuit (M) that controls the selectors based on a set-up value of delay time and an error in delay time of each delay equipment. In order to provide a delay time which is equal to a multiple of a predetermined time unit in spite of an error in delay time of each delay element, either a correction matrix is connected in series to the matrix or the weight of each delay element is modified.