A bipolar random access memory array including "end of write shut down circuit means" coupled to the write circuit means is disclosed. The "end of write shut down circuit means" is activated by and only functions as the written cell switches state. The "end of write circuit means" is coupled between the opposite bit line and preferably the write transistor of a write circuit of the write circuit means. The use of "the end of write circuit means" improves the overall operation of the memory and in particular the write operation thereof.
A memory device that does not need to be refreshed and that has a relatively small size. The memory device includes a memory cell having a first PNP transistor, wherein an input voltage is provided to its base and its emitter is ground and a second NPN transistor having its base connected to the collector of the first transistor and its emitter connected to a power source, and wherein the collector of the second transistor is connected to the base of the first transistor.
