A clock signal generator for creating an output clock signal with fifty percent duty cycle and multiple of the input clock signal frequency allows generation of such a signal independent of input signal frequency and duty cycle. The generator utilizes an adjustable-delay oscillating feedback loop. A serial array of propagating delay elements measure the period of the input clock signal by triggering on successive input clock signal leading edges. This propagation lengthens the oscillating feedback loop until the output signal matches the desired frequency multiple. The feedback loop automatically adjusts according to a predetermined fraction of the period of the input clock signal. A fixed ratio of feedback loop delay to serial array delay ensures an output signal with a desired frequency multiple of the input signal frequency. Incorporation of an inverting logic gate in the oscillating feedback loop ensures a half-wave output clock signal having a fifty percent duty cycle.

In a pulse duty ratio discrimination circuit for discriminating duty ratios of input signals by comparing a count value with a threshold value through means of counting, with a counter using clocks, a time period starting with a reference level changing point occurring every predetermined period in the input signal and ending with a level returning point, the present invention is characterized by a pulse duty ratio discrimination circuit that includes not only period determination means for determining the periods of the input signals by resetting the count value of the counter at the period of the input signal and by comparing actual count values for a plural number of count patterns of the counter established in advance, but also clock selection means for selecting the frequency of the clock based on a determination result of the period determination means.

A system and method counts the maximum and minimum number of continuous cycles in which a RISC system event occurs. Additionally, a hold enable input offers the functionality of counting max/min events that are not continuous in time. These maximum and minimum counts are useful for benchmarking performance measurements and for performance debugging. The system and method provides a self-test mode for component testing, as well as maximum, minimum, and accumulator counting modes for use in a programmable performance analysis system. These counting modes allow various aspects of a target system to be categorized for performance analysis. The system has applicability in workstations and RISC systems having high frequency requirements typically greater than 50 Mhz. In one embodiment, a programmable system designed to be utilized in a workstation environment makes use of two identical full speed clock counters and a comparator which are controlled by a PAL that implements a state machine to provide the above four modes of operation.

A voltage conversion circuit has a pulse generator that generates a pulse signal having a fixed pulse width and a variable pulse period. The output voltage of this voltage conversion circuit is determined according to the ratio of the pulse width to the pulse period of the pulse signal generated by the pulse generator. This circuit configuration makes it possible to produce as the output voltage lower voltages than ever.

A voltage conversion circuit has a pulse generator that generates a pulse signal having a fixed pulse width and a variable pulse period. The output voltage of this voltage conversion circuit is determined according to the ratio of the pulse width to the pulse period of the pulse signal generated by the pulse generator. This circuit configuration makes it possible to produce as the output voltage lower voltages than ever.