An image data processor comprises a memory for storing image data, an image data processing unit for processing the image data stored in the memory, and an address calculation unit operating in parallel with the image data processing unit for calculating the addresses of the image data and controlling input/output to and from the image data processing unit. The image data processor can execute processings of image data such as extraction, deletion, synthesization or the like of the image data at a high speed.
A high speed image processing apparatus comprising a central processing unit and a memory to store images wherein a program directs the central processing unit to perform a poly-point operation on image data. Poly-point operations filter images without multiplication or division yet achieve versatile filter characteristics. Poly-point operations accomplish linear or non-linear filter operations quickly and allow complex image processing operations on general purpose computing apparatus.
The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.
An image processing method using memory management and pre-computed look up tables to speed up computations. Application of filters along directions other than image rows is simplified using several structured processing approaches that improve image data cache-ability. Time consuming or repeated computations are pre-computed and stored as look up tables to reduce the time required for image processing and to remove or reduce the need for special purpose image processing hardware.
An image processing apparatus has plural memories each capable of storing image data of a picture frame, and combines the image data of the plural memories. A data bus transmits the output resulting from the combining, to the input of the plural memories.
The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.
