A method for filtering a time signal (e(t)) sampled in blocks of N samples (e(n),e(k)) uses a transfer function defined in the frequency domain by LN samples (H(K)). The transfer function is filtered by a time window (g1) of width N, and a frequency subsampling of ratio N is performed to give a partial transfer function defined over N samples (H1(k)). The method enables the complexity of circuits operating in real time to be optimized. The technique is particularly suitable for correcting long echoes in television picture receivers.

In a diagnostic process in which two images are made on an image recording medium of the same structure at the beginning and the end of a time interval during which the structure changes, a method is provided for permitting a computing device to improve the alignment of the images as reproduced in the form of pixels on a monitor screen. A particular spatial pattern of marker elements is provided, when each of the images is made, in a particular juxtaposition to the structure being imaged, so that the shadows of the elements arise on the respective images. The computing device can then rotate, translate and alter the scale of one image with respect to the other until the shadows of the elements on one image coincide as closely as possible with those on the other image.

A finite impulse response (FIR) filter is provided for shaping a one bit serial digital data pulse train in a digital data transmission system. The filter comprises (i) a delay element for sequentially receiving binary data bits in the data pulse train at fixed data cycle intervals and outputting simultaneously in parallel a plurality n of data bits representing a most recent history of the past n data bits received by the delay element during the past n data cycle intervals; (ii) a sampling element for sampling the data pulse train at a rate of m samples per bit, and (iii) a memory device having at least (n 30 m) address lines for providing at least 2.sup.(n+m) address locations. The n data bits and m samples provide an input to the address lines, the memory device in response providing a specific precomputed and stored output value for each possible combination of address line inputs. The delay element may be implemented as a shift register and the memory device may be implemented as at least one programmable read only memory (PROM) integrated circuit. A counter circuit determines the beginning of each fixed data cycle interval and the rate at which said fixed data cycles occur, which rate is between 500 kilobits (Kbs) and sixteen megabits per second (Mbs). The filter operates as a 319 tap FIR filter at a data input rate of 500 Kbs and as a 19 tap FIR filter at a data input rate of 16 Mbs.

A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.

The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.