A fixed pattern signal storage and replay system in which the silent periods of the signal are not stored but regenerated. During the silent periods of the signal, which is pulse code modulated, the decoder for the storage memory is inactivated.
The present invention relates to a method and apparatus for recording an audio signal on an integrated circuit (IC) memory card. The audio signal to be recorded is considered to have plural chapters (i.e., songs, or distinct movements) with a mute section (i.e., moment of silence of at least a predetermined length) between each adjoining chapter in the audio signal to be recorded. The present invention provides for automatic partitioning between the chapters as they are recorded on a data area of the IC memory card even when the audio signal is recorded continuously based upon a single press of the record button and terminated with a single press of the stop button. Since the chapters of the recorded audio signal are automatically partitioned, without need for starting and stopping of the recording process by a user, a recording is conveniently made on the IC memory card which allows random access to any one of the chapters for playback. Also, the present invention provides for the function of editing the table-of-contents (TOC) area of the IC memory card so as to correct the partitioning information recorded in the TOC area of the IC memory card.
A method for playback of speech in an audio recording. The method comprises performing full word-level recognition of the speech including recognition of silent pauses and filled pauses, suppressing playback of the filled pauses and silent pauses, alerting a listener of the audio recording to locations of suppressed filled pauses and silent pauses during playback of the audio recording, and accepting a user command to disable suppression of any filled pause or silent pause during playback of the audio recording.
The method of recording and reading audio information signals in digital form includes detecting, during time compression of digital signals, a chain of code values of the digital signal corresponding to a pause in the audio signal, measuring the duration of this chain of code values of the digital signal and shaping a pause identifier code and a pause duration code for subsequent recording with the digital signal. Furthermore, in the reading mode, time decompression of the digital signal includes detecting the pause identifier code and the pause duration code and using them to restore the duration of said chain of code values of the digital signal. To perform this method, the apparatus comprises a pause decoder (17), a pause identifier code shaper (18), a pause identifier code decoder (19), a condition (20) of pause duration count control signals and a pause duration counter (21).
A speech synthesizer includes a data memory having a plurality of address areas, which stores a plurality of phases in the address areas and an address designating circuit designating one of the address areas based on the phase signal. Further, a speech synthesizer includes a speech synthesizing circuit generating a speech synthesizing signal corresponding to the phase, which is stored in the designated area, a digital/analog converter transforming the speech synthesizing signal to an analog signal having amplitude, and a counter setting a period of silence. Furthermore, a speech synthesizer includes a silence-input circuit being connected between the speech synthesizing circuit and the digital/analog converter, which supplies a predetermined voltage to the digital/analog converter for the period that is set by the counter.
A multi-mode integrated circuit structure. In one embodiment, an integrated circuit structure includes a first die having at least one first component disposed on a face, the first die fabricated using a first process that is optimal for operating the component in an first mode and a second die stacked on the first die, the second die having at least one second component disposed on a face and the second die fabricated using a second process separate from the first process that is optimal for operating the second component in a second mode. As such, the integrated circuit structure provides an electronic device with a single integrated circuit structure for performing operations optimally in more than one mode, such as operations in enhancement mode and operations in depletion mode.