A shared memory computer method and apparatus having a plurality of sources, a memory manager, and memory units in which the memory locations of data items are randomly distributed. The memory manager includes a translation module for locating data items in the memory units and a temporary storage buffer for storing at least a portion of messages between sources and the memory units with respect to data items.
This application is a division of application Ser. No. 254,583, filed Apr. 15, 1981, now U.S. Pat. No. 4,484,262, which is a continuation of Ser. No. 002,004, filed Jan 9, 1979, now abandoned.
A storage medium unit is used as a part of a system for providing information-on-demanding service. The storage medium unit has a storage device for storing information data including video data and/or audio data to be retrieved therefrom and transmitted to end user devices of the information-on-demand service, a memory controller for controlling the storage device, and a memory device for storing software program. The software program is downloaded from a system manager of said system into said memory device. The memory controller controls operation of the storage device according to the downloaded software program.
Hierarchical multiprocessors systems with common level expansion modules. The invention includes an architecture for such multiprocessor system. One facet of such multiprocessor system including a memory control system for minimizing duplicate read requests comprising: a plurality of processing systems; a bus connecting the processing systems; a memory for storing variables; circuitry operable for receiving read requests through the bus from other processing systems; a memory for queuing incoming read requests, wherein the memory for queuing incoming read requests is connected to the circuitry operable for receiving read requests; a memory for queuing outgoing read requests, wherein the memory for queuing outgoing read requests is connected to bus and the memory for storing variables; and circuitry for comparing the incoming read requests to the queued read requests, wherein the circuitry ignores duplicates of a first read request prior to the first read request leaving the memory for queuing outgoing read requests.
A multiport memory system has a plurality of data input/output ports, a plurality of memory banks, and a switching network for connecting the ports and the memory banks. A page address is transferred by way of a data line of the switching network and an address calculation is performed in each memory bank so that data can be read out of and written in to continuously via the plurality of ports.
A method for enhancing concurrency in a multiprocessor computer system is described. Various tasks in a computer system communicate using commonly accessible mailboxes to access valid data from a location in the mailbox. A task holding the valid data places that data in a mailbox, and other tasks read the valid data from the mailbox. The task that inputs the valid data into the mailbox is caused to notify other tasks addressing the mailbox that the valid data is contained therein. Thus, no central coordination of mailbox access is required. Further, busy waits for valid data are minimized and the ressources of tasks and processors are used more efficiently. By coordinating several lists associated with each mailbox, conflicts in accessing data and delays in obtaining data are also minimized.
A system and method for piggybacking read responses on a shared memory, multiprocessor bus having a plurality of nodes coupled to the bus. The system determines whether a pending read request from a first node targets data required by a subsequent read request from a second node. The system then piggybacks a read response corresponding to the pending read request by permitting the first and second nodes to share the required data without transmitting the subsequent read request on the bus or otherwise generating any additional bus traffic. The system also supports piggybacking of multiple simultaneous read transactions to different addresses.