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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of power controller
apparatus for electrical and electronic equipment, and more particularly
to time delay power controller apparatus for such equipment.
2. Discussion of the Prior Art
It is well known by electrical engineers and most users of electrical of
electronic equipment that when a piece of such equipment is turned on, a
high turn-on electric current is caused in the equipment. Within several
seconds, usually less than about 2-4 seconds, the turn-on current spike
decays to a steady state, operating current. The turn-on current spike is
caused by the charging of cooperative elements or portions of the
equipment and is dependent upon the rate of electrical charging of the
equipment, as given by the differential equation:
I=dQ/dt,
wherein I is the current and dQ/dt is the time rate of charging.
From the above equation it can be seen that a fast equipment turn-on, in
which dQ/dt is high, gives rise to a high current spike. Typically, the
turn-on current spike is several times higher than the steady state or
average current drawn by the equipment subsequent to turn-on.
The combined effect of individual high turn-on currents of each of several
or a number of pieces of electrical or electronic equipment is that the
current carrying capacity of existing building electrical circuits into
which the equipment is connected may be exceeded. This then causes circuit
breakers to trip open at the instant the equipment is turned on, thereby
shutting down all the equipment. This may occur even though the building
circuit may have capability for safely handling the combined steady state
operating currents of the equipment.
In some instances where several different building electrical circuits are
conveniently available, the possibility of overloading individual ones of
the building circuits may be avoided by connecting different pieces of
equipment into separate circuits. However, a multiplicity of separate
building circuits is typically not available in a single room where a
number of pieces of electrical or electronic equipment, for example, a
computer and several associated disc drives, are located. The installation
of several independent building circuits to service several pieces of
electrical equipment may be very costly.
Although sometimes possible to do so, it is generally not feasible to
substantially reduce turn-on current spikes by increasing the equipment
turn-on time. For example, a slow rate of applying voltage might be
damaging to many types of electrical equipment and motors.
As a consequence of high turn-on current problems associated with the
simultaneous turning on of several pieces of electrical equipment, it is
usually preferable to turn on just one piece of equipment at a time, with
the interval between the turning on of successive pieces of equipment
being sufficient to assure that the current drawn by one piece of
equipment has dropped from its high turn-on level to its normal operating
level before the next piece of equipment is turned on. The following of
such a time delay turn-on procedure generally permits several pieces of
electrical equipment to be operated from a single building circuit without
overloading the circuit.
However, the manual turn-on sequencing of several pieces of equipment is,
itself, generally unsatisfactory. This is because the required time
interval between the successive turn-ons is difficult to manually control.
Also it may be necessary or desirable to always follow the same,
predetermined turn-on sequence for a particular system of interacting
electrical equipment. The following of a predetermined specific turn-on
sequence may be difficult to assure by manual turn-on procedures, and
out-of-sequence equipment turn-ons may cause system malfunctions, for
example, loss of data in a computer system.
Because of such high current turn-on problems, specialized power controller
equipment has been developed which typically provide both an instantaneous
power output and a single time delayed power output or time delayed output
signal. If, however, multiple time delays are required, as is the case
with computer systems having a main frame computer and two or more data
storage disc drives, it has been necessary to cascade two or more of the
available power controllers in such a manner that one power controller
provides a time delayed signal to another power controller to start its
operation, and so on.
Several disadvantages are, however, associated with the use of such
cascaded power controllers. For example, the use of several independent
power controllers is expensive and the several power controllers require
the use of often limited rack space. Also there is the problem of
maintaining the several power controllers in the proper operating
relationship relative to one another; particularly if any of the power
controllers are temporarily disconnected for servicing. Still further, an
excessive amount of equipment interwiring is required which may, in and of
itself, result in electrical malfunctions or reduced operational
reliability. Still further, each of the power controllers requires its own
power source and the building wiring may not provide sufficient electrical
outlets to accommodate the various power controllers.
To the knowledge of the present inventors, a multi-time delayed power
controller has not, heretofore, been available. One reason for such
availability is believed to be the difficulty in providing multiple
internal delays to power outlets in a single, economical power controller.
For these and other reasons, a need exists for time delay power controllers
with two or more internal delays and which provide two or more delayed
power outputs capable of powering other electrical equipment.
SUMMARY OF THE INVENTION
Time delay power controller apparatus, in accordance with the present
invention, comprises a power stage and means adapted for connecting the
power stage to a conventional power source, a plurality of time delayed
outputs, a D.C. voltage bus and a ground, a D.C. power supply connected to
the D.C. bus, and a plurality of time delay timing stages connected
between the D.C. bus and ground.
Each of the timing stages includes, a timer initiating voltage input line
connected to the timer, a time delay voltage output line and a control
relay connected to a corresponding one of the time delayed outputs and
having an energizing coil connected to the time delay voltage output line.
Further included in each of the timing stages are timing means connected
between the timer initiating voltage input line and the time delay voltage
output line, for causing, a predetermined time interval after a change in
voltage stage appears on the timer initiating voltage input line, a
voltage state change on the time delay voltage output line. The voltage
state change on the time delay voltage output line causes the energizing
of the associated control relay coil and thereby causes a time delayed
control signal to be provided by the control relay to the corresponding
one of the time delayed outputs. Means are provided for interconnecting
the time delay timing stages in electrical series with one another, with
the time delay voltage output line of each timing stage, except the
last-in-sequence one, being connected to the timer initiating voltage
input line of the next-in-sequence one of the timing stages.
Means are additionally provided for changing the voltage state on the timer
initiating voltage input line of the first-in-sequence one of the timing
stages so as to start time delaying operation of the apparatus and
increasing-in-time delay control signals to be applied to successive ones
of the time delayed outputs.
The time delayed outputs may comprise time delayed power outputs adapted
for providing electrical power to electrical equipment connected thereto,
and including means responsive to the time delayed control signal received
from a corresponding one of the timing stage control relays for connecting
the power output to the power stages so that electrical power is applied,
in a time delayed sequence, to the time delayed power outputs. In an
embodiment, each of the time delayed power outputs include a normally open
power relay electrically connected between the power output and the power
stage, the relays being closed by the time delayed control signal from a
corresponding one of the timing stage control relays so as to connect the
power output to the power stage.
It is preferred that each of the control relays is a normally open relay
and that one side of the control relay coil of every other one of the
timing stages is connected to the D.C. bus and one side of the control
relay coil of intermediate ones of the timing stages is connected to
ground. Also preferably, there are at least two time delayed timing
stages.
In one embodiment of the invention, means are included for turning on the
apparatus, there being a non-time delay power output connected for
receiving power from the power stage when the apparatus is turned on.
Also, the means for changing the voltage state on the timer initiating
voltage input line of the first-in-sequence one of the timing stages also
changes the voltage state in response to the apparatus being turned on.
Advantageously, the apparatus may include a first, non-time delay power
output and means for applying power from the power stage to the first
power output. The time delay outputs may comprise second and third, time
delay power outputs, each of which include means responsive to the time
delay control signal provided thereto by the corresponding one of the
timing stage relays for connecting the second and third power outlets to
the power stage. The means for changing the voltage stage on the timer
initiating voltage input line of the first-in-sequence timing stage is
responsive to the means for applying power to the first power output for
simultaneously providing the voltage state change to the first-in-sequence
one of the timing stages. In an embodiment, the power stage is connected
to a conventional, 208 volt, 3 phase power source and provides power from
different ones of the 3 phases to different ones of the first, second and
third power outputs.
Preferably, the time delay intervals provided by the timing stages are
substantially equal to one another, such time delays being preferably
between about 2 to about 6 seconds and more preferably about 4 seconds.
BRIEF DESCRIPTION OF THE DRAWINGS
A better understanding of the present invention may be had from a
consideration of the following detailed description, taken in conjunction
with the accompanying drawings in which:
FIG. 1 is a generalized, functional block diagram showing the time delay
power controller apparatus of the present invention to which are shown
operatively connected, by way of illustration, a plurality of power
equipment controlled by the apparatus;
FIG. 2 is an electrical schematic drawing of the time delay power
controller apparatus of FIG. 1 showing a plurality of time delay timing
stages;
FIG. 3 is a timing diagram showing voltages at points of the time delay
timing stages and showing typical current requirements of exemplary
electrical equipment connected to time delay power outputs of the time
delay power controller apparatus, FIG. 3a showing voltages in the first
timing stage, FIG. 3b showing voltages in a second timing stage and FIG.
3c showing voltages in a third timing stage.
FIG. 4 is a diagram showing output power relay portions of the apparatus
and showing time delayed power outputs provided thereby, FIG. 4a relating
to a "Master (non-time delay) power output, FIG. 4b relating to a "Delay"
power output, FIG. 4c relating to a "Delay 2" power output and FIG. 4d
relating a "Delay 3" power output; and
FIG. 5 is a partial schematic drawing showing connection of the apparatus
of FIG. 1 to a 208 V, 3 phase power source.
DESCRIPTION OF THE PREFERRED EMBODIMENT
There is shown, in block diagram form, in FIG. 1 an examplary electronic or
electrical system 10, in which a multiple time delay power controller
apparatus 12, according to the present invention, may be used to
advantage. As more particularly described below, apparatus 12 is
configured, and is operative, for controlling other pieces of electrical
or electronic equipment (E.C.) such as those E.C.'s designated, by way of
illustrative example, in FIG. 1 by the reference numbers 14, 16, 18, 20
and 22, E.C.'s 20 and 22 being shown in phantom lines for reasons to
become apparent.
In general, the function of apparatus 12 is to provide timed delayed
outputs to E.C.'s such as E.C.'s 14-22 (FIG. 1). In addition, one or more
non-time delayed outputs may, for convenience or other purposes, be
provided by apparatus 12. The time delayed outputs (as well as some or all
of the non-time delayed outputs) may be of the power-type or of the
signal-type.
However, for illustrative purposes, apparatus 12 is shown in FIG. 1 as
having both power-type and signal type outputs. Accordingly, E.C.'s 14, 16
and 18 are shown to be directly powered, through respective power lines
30, 32 and 34, from apparatus power outputs 36, 38 and 40, respectively.
In addition, E.C.'s 20 and 22 are shown to be connected by signal lines 42
and 44, respectively, to apparatus control signal outputs 46 and 48.
Apparatus 12 may thus provide operating signals to E.C.'s 20 and 22, which
are separately connected, by respective power lines 50 and 52 to power
plugs 54 and 56.
Power is provided to apparatus 12 from an existing building electrical
outlet 66 through a power cord or line 68. Building outlet 66 may,
according to one version of apparatus 12 involved, be selected to provide
conventional 110 volts A.C. power, or may, as more particularly described
below, be selected to provide 208 volts, 3 phase power.
For purposes of further describing the invention, it will be hereinafter
below considered that apparatus 12 provides only power-type outlets 36, 38
and 40. It is, however, to be understood that, as discussed above, the
invention is not limited thereto. The same general principals of
construction and operation of apparatus 12 are applied whether its outputs
are of the power-type or of the signal type, as will be apparent from the
following description.
As shown in the circuit schematic drawing of FIG. 2, apparatus 12 comprises
generally a power portion or stage 74, which is connected by line 68 to
building power outlet 66; a D.C. power supply 76; an emergency shut off
stage 78; an actuating or turn-on stage 80; a relay stage 82; first second
and third timing delay stages 84, 86 and 88, respectively, and an output
stage 90.
Described functionally, power stage 74 provides A.C. power to other
portions of apparatus 12, including, in the present embodiment, output
stage 90. D.C. power supply 76 provides D.C. voltage, for example, about
12 volts D.C., to timing delay stages 84, 86 and 88 for the operation
thereof. Emergency shut-off stage 78 causes an automatic shut off of
apparatus 12 in the event an associated emergency line 92 is grounded.
Actuating stage 80 is operative for turning on apparatus 12 and for
thereby starting the time delay sequencing described below. Timing delay
stages 84, 86 and 88 provide a sequence of time delayed signals which,
through relay stage 82, control output stage 90.
For illustrative purposes, apparatus 12, as illustrated in FIG. 2 and as
more particularly described below, provides a single, non-time delay
out-put identified on such Figure as "Master" and first, second and third
time delayed outputs, identified as "Delay 1", "Delay 2" and "Delay 3".
The "Master" and three "Delays" correspond generally to outputs 36, 38, 40
and 46 of FIG. 1. Although only first, second and third timing delay
stages 84, 86 and 88 are shown in FIG. 2, it will be apparent from the
following description that additional, in series timing delay stages (not
shown) can readily be provided downstream of third stage 88 according to
particular commercial or customer needs. It will also become apparent from
the following description that the first, second and third timing delay
stages 84, 86 and 88 are not identical, but that odd (i.e., first, third,
fifth, seventh, . . . ) stages, only first and third stages 84 and 86 of
which are shown are configured the same as one another and that even
numbered stages (i.e., second timing, fourth, sixth, eighth, . . . stages,
only the second stage 86 of which is shown) are configured the same as one
another. There are important differences between odd and even numbered
stages, as is discussed below.
Described more specifically, D.C. power supply 76 is constructed with a
conventional transformer 98, which receives power from power stage 74, two
diodes 100 and a capacitor 102. The capacitance of all capacitators shown
in FIG. 2 being in microfarads unless otherwise noted on such Figure.
Components of power supply 76 are selected to provide about 12 V D.C.
voltage, through emergency shutoff stage 78, to a relay coil 104 (also
designated as K2 in FIG. 2). Turning on of a switch 106 of actuating stage
80 energizes relay coil 104, thereby causing closing of normally open
relay contacts 108 in actuating stage 8u0 and the providing of +12 volts
D.C. to a D.C. voltage bus 110 which extends in electrical series through
timing delay stages 84, 86 and 88 (as well as any additional timing stages
which may be connected downstream of the third in-series stage 88).
Accordingly, and as shown in FIG. 2, timing delay stages 84, 86 and 88 are
each connected between bus 110 and ground and are, as described below,
connected in electrical series.
The described energizing of relay coil 104 also causes closing of relay
contacts 112 which thereby causes a D.C. voltage to be applied, through
line 114, to the non-time delayed "Master" output. Thus, the turning on of
apparatus 12 by switch 106 energizes D.C. bus 110, to start sequential
operation of timing stages 84, 86 and 88, as described below, and
simultaneously causes a control volage to be applied to the non-time
delayed "Master" output.
First timing stage 84 comprises an R-C circuit 116, connected between D.C.
voltage bus 110 and ground, a type 555 timer integrated circuit 118 and a
normally open control relay 120 having an energizing coil 122, one side of
which is connected to ground. Type 555 circuit 118 is connected between
R-C 116 and a time delay voltage output line 124 to which is connected the
other side of relay coil 122.
Configuration of first stage 84 is such that at time t.sub.o when D.C.
voltage from power supply 76 is provided to bus 110 by closing of relay
contacts 108, the voltage provided to one side (pins 2 and 6 as shown in
FIG. 2) of type 555 circuit 118 non-instantaneous increases from 0 volts
to bus voltage, the voltage increase time being equal to the time delay
interval .DELTA.t.sub.a, provided by R-C circuit 116. Time delay voltage
output line 124 is connected, through a diode 126, to a timer initiating
voltage input line 128 of second timer stage 86 in such manner that at
time, t.sub.o, such output line is at ground potential, relay coil 122
being thereby non-energized. After time interval, .DELTA.t.sub.a, at time
t.sub.1, when the voltage at pins 2 and 6 of type 555 circuit 118 reaches
a preselected voltage, for example, about 2/3 D.C. bus voltage, such
circuit causes the voltage state on output line 124 to abruptly change
from 0 to bus voltage, thereby energizing relay coil 122 and causing
contacts 128 of relay 120 to close. The voltage state on output line 124
thereafter remains the same (at D.C. bus voltage) and relay contacts 128
remain closed until apparatus 12 is turned off. Relay contacts 128 are
connected to D.C. bus 110 to thereby apply D.C. bus voltage to "Delay 1"
output when such contacts are closed. Thus, at time t.sub.1, after initial
time delay, .DELTA.t.sub.a, a D.C. voltage "signal" is applied, through
relay contacts to, "Delay 1" output, such D.C. signal being maintained
until apparatus 12 is turned off by operation of switch 106.
Second timing stage 86 is similar to the above-described first timing stage
84 and comprises an R-C circuit 138, a type 555 140 and a normally-open
control relay 142 having an energizing coil 144. A time delay voltage
output line 146 is connected to an output (pins 3) of type 555 circuit
140, input pin 2 and 6 of such circuit being connected to R-C circuit 138
and pins 4 and 8 being connected to D.C. Bus 110.
A principal and significant difference between second timing stage 86 and
first timing stage 84 is, however, that second stage relay coil 144 is
connected between time delay voltage output line 146 and D.C. bus 110,
instead of between such output line and ground as is first stage relay
coil 122. As is apparent from FIG. 2, voltage output line 146 goes to D.C.
Bus voltage when D.C. bus 110 is energized. As a result, relay coil 144
remains unenergized and contacts 148 (in relay stage 82) of relay 142
remain open until second timing stage 86 times out. R-C circuit 116 and
type 555 integrated circuit 118 function together as a timing circuit (or
means), the R-C circuit providing a ramping voltage which causes or
enables the associated type 555 circuit to change the voltage stage on
line 124 when the voltage provided by R-C circuit 116 ramps up to a
preestablished level.
As described above with respect to first timing stage 84, time delay
voltage output line 124 thereof, which is electrically connected through
diode 126 to timer initializing voltage input line 128 of second timing
stage 86, remains at ground potential until R-C circuit 116 and circuit
118 time out (at time t.sub.1) at that time, type 555 circuit 118 flips
the voltage state on output line 124 to D.C. bus voltage. Such flipping of
voltage states on output line 124 tu | | |
