Communications system having an addressable receiver

We claim:

1. An addressable receiver for receiving a composite video and digital data signal, transmitting video output signals and controlling external devices, comprising:

a. means for processing the composite video and digital data signal into a first video signal available for receiver output, a synchronization signal available for receiver output and a serial digital data stream for controlling the receiver,

b. means for processing the digital data stream to recognize within such stream control words,

c. means for storing digital data contained in the digtal data stream,

d. means for converting stored digital data into a second video signal containing characters and available for receiver output,

e. means responsive to the control words for controlling the receiver output.

2. An addressable receiver in accordance wiht claim 1, further comprisng means for combining the first and second video signals into an output signal.

3. An addressable receiver in accordance with claim 1, further comprising:

a. means for receiving a third video signal,

b. means for combining the first or third and the second video signals into an output signal, and

c. means for retransmitting the synchronization signal.

4. An addressable receiver in accordance with claim 1, further comprising:

a. means for processing at least one of the control words into at least one control signal, and

b. means for transmitting said at least one control signal.

5. An addressable receiver in accordance with claim 1, further comprising:

a. means for receiving a second data

b. means for processing the second data signal into a fourth video signal containing characters, and

c. means for combining the first or third and either or both the second and fourth video signals into an output signal.

6. An addressable receiver in accordance with claim 1 further comprising means for recognizing with the digital data stream hierarchical addresses and controlling the means for storing digital data addressed to said receiver in accordance with the hierarchical address preceding such data.

7. An addressable receiver in accordance with claim 1, further comprising means responsive to a flag contained in the digital data for causing the receiver immediately to alter its output signal.

8. An addressable receiver in accordance with claim 7 further comprising means responsive to the flag for combining an audio tone with the receiver output signal.

9. An addressable receiver in accordance with claim 1, further comprising means responsive to interruption of receipt of the composite signal for transmitting a predetermined video output signal;

10. An addressable receiver for receiving a composite video and digital data signal, transmitting video output signals and controlling external devices comprising:

a. means for processing the composite video and digital data signal into a first video signal, a synchronization signal and a serial digital data stream,

b. means for processing the digital data stream to recognize within such stream control words,

c. means for processing the digital data stream to recognize within such stream heirarchical addresses and for storing digital data addressed to said receiver accordance with an heirarchical address proceeding such data,

d. means for converting stored digital data into a second video signal containing characters, which signal is synchronized with the synchronization signal,

e. means for receiving a third video signal,

f. means for processing at least one of the control words into at least one command signal,

g. means for receiving a second data signal,

h. means for processing the second data signal into a fourth video signal containing characters,

i. means for combining the first or third and either or both the second and fourth video signals into an output-available signal,

j. means responsive to the control words for transmitting, as the receiver output, the synchronization signal, th ecommand signal and the output-available signal,

k. means responsive to a flag contained in the digital data for overriding said transmitting means responsive to the control words to cause the receiver immediately to alter its output signal, and

l. means responsive to interruption of receipt of the composite signal for transmitting a predetermined video output signal.

11. An addressable receiver in accordance with claim 10, wherein said means (b), means (c), means (d), means (f), means (j), means (k) and means (l) include a programmable device.

12. An addressable receiver in accordance wiht claims 1 or 10 including at least one programmable device for controlling operation of a portion of the receiver.

13. An addressable receiver in accordance with claim 1, wherein each of said means for processing and for controlling is controlled by at least one programmable device.

14. A communication system comprising a teletext transmitter and a plurality of addressable receivers adapted to receive teletext transmissions from the transmitter, and, responsive to hierarchical addresses contained in such transmissions, process selected portions of such transmissions, in which system the hierarchical addresses define a plurality of hierarchical group levels in addition to the level comprising all the receivers and the level comprising only one receiver, such that receivers in subgroups of a hierarchical group level may be addressed by addressing that group level.

15. A process for retransmitting data messages comprising the steps of simultaneously:

a. receiving with a first receiver a first transmission containing, in the following order:

a first control word,

a first address field,

a first data message,

a second control word,

a second address field,

a second data message; and

at least one subsequent control word;

b. storing the first data message in the first receiver as it is received and retransmitting the first data message with the first receiver upon receipt of at least one of the subsequent control words; and

c. receiving with a second receiver the first transmission, storing the second data message in the second receiver as it is received and retransmitting the second data message with the second receiver upon receipt of at least one of the subsequent control words.

16. The process according to claim 15 further comprising the steps of:

a. receiving a second transmission together with the first transmission;

b. continuously retransmitting the second transmission with each of the receivers; and

c. upon receipt of a subsequent control word, combining the respective data message retransmitted by each receiver with the retransmitted second transmission.

17. The process according to claim 15 and claim 16, further comprising the steps of:

a. receiving analog data with at least one of the receivers;

b. processing the analog data into a third signal within the one receiver; and

c. upon receipt of one of the subsequent control words by the receiver, combining the third signal with the transmission then being transmitted by the receiver.

18. The process according to claim 15, further comprising the steps of:

a. receiving with the first receiver the first transmission further comprising a third data message containing a flag; and

b. immediately retransmitting the third data message from the first receiver responsive to the flag.

19. The process according to claim 17 further comprising the steps of:

a. receiving with the first receiver the first transmission further comprising a third data message;

b. storing the third data message in the first receiver as it is received, and

c. retransmitting the third data message serially with the first data message upon receipt of one of the subsequent control words.

Description Submit all comments and votes

Reference is made to the Microfiche Appendix which forms a part of this document and is incorporated herein by reference. The Microfiche Appendix comprises 244 frames located on 3 microfiche.

BACKGROUND OF THE INVENTION

This invention relates to a communications system for transmission of audio and combined video, data and control signals to remote receiving locations for retransmission under the command of the control signals.

Transmission of audio and video signals to local receiving stations for immediate use, rebroadcast or recordation for later broadcast is well established practice, particularly in connection with distribution of television programming by various television networks. Utilization of data to generate characters which are displayed on a video screen over a single color background or another video signal background is also established practice.

However, expansion in the availability of data of both general and specific interest to various groups of data consumers and the need for a system capable of efficiently transmitting such data to specific remote locations and to control the further broadcast, display or transmission of such data at those locations have resulted in the need for audio, video and data transmission systems with associated control capabilities not previously available.

SUMMARY OF THE INVENTION

The present invention comprises a communications system utilizing a novel hardware and software configuration simultaneously to transmit conventional video and audio program material and data and control commands within the constraints of conventional television signal specifications (such as National Television System Committee (NTSC) standards) to remote signal processors or receivers within the system which receive the entire transmission and process it in a predetermined manner such that the data and conventional video and audio signals may be utilized at the remote receivers, under network control, particularly for broadcast on a local cable television system.

The system of the preferred embodiment of the present invention transmits, typically utilizing a satellite transponder, a first conventional video and audio television signal together with a digital data stream transmitted in the vertical blanking interval of the first video signal. The data stream in the first video signal comprises digital control and address data and digital text data. A local receiver according to the preferred embodiment may process and retransmit the first video (and audio) signal and, utilizing a character generator as discussed below, may store the digital text data and process it into a second ("satellite" text) video signal containing text for transmission. In addition, the receiver may receive and retransmit a third video (and audio) signal from a local source such as a video recorder, so that local commercials or other material may be displayed, and it provides a synchronization signal which may be input to the local source to synchronize signals from it with other video signals processed or generated by the receiver. So that local cable operators may also be able to compose and display textual data, the receiver may also receive digital data from a keyboard. This data, as well as data from local weather sensors, is processed by the receiver into a fourth video signal containing text. On command from network control, the receiver may select for output the first satellite video (and audio) signal, the third local video (and audio) signal, or a solid color background video signal, and may combine with any of these signals the second (satellite) and/or fourth local textual video signals.

The digital control and address data in the data stream of the first video signal control the operating states, or modes, of the receiver of the preferred embodiment and determine the video, audio and other outputs of a particular receiver. Control data sent in the "Output Mode Control Word" ("OMCW") of the data stream determine, among other things, which video signals or combinations thereof will be presented and which audio signals will be presented, by controlling whether satellite video, local video, or character generator input will be processed and sent by the receiver.

The address words of the data stream and the control words following them allow each receiver or a group of receivers to accept, store and process particular text data and to display this text in a particular format. Thus, different digital text data may be sent to different receivers and groups of receivers for simultaneous presentation in response to the OMCW control data which controls timing of such presentation.

The referred embodiment of the present invention herein described may be utilized for a network of local affiliates receiving transmissions from a single source dedicated to television programming related to weather information and advertising. Accordingly, the hierarchy of addressability utilized in the described embodiment contemplates geographic organization of local receivers consistent with weather patterns, and the data sensors input to the local receivers may be weather sensors. However, as will be apparent to those skilled in the art, the invention may also be adapted to use for transmission of entirely different programming and data for other types of commercial broadcasting and for noncommercial communications, including teletext only communications, and aspects of the invention may be adapted to other uses such as various remote control networks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-3 and 3A are a block diagram of the receiver of the present invention.

FIGS. 4-39 are detailed schematic diagrams of the receiver shown in FIGS. 1-3, not including the power supply.

FIG. 40 is a block diagram of the data framing scheme for a page header for a text page of data for transmission in accordance with the preferred embodiment of the present invention.

FIG. 41 is a diagram similar to FIG. 40 for any text page row 1-9.

FIG. 42 is a diagram similar to FIG. 40 for a date/time row.

DETAILED DESCRIPTION OF THE DRAWINGS

A. Hardware

FIGS. 1 through 3 are a block diagram of the preferred embodiment of the receiver 110 of the present invention. This diagram can be divided for purposes of description into three groups of sections: the teletext group, the control group, and the video group. FIGS. 4-39 are schematic diagrams of portions of receiver 110, and those figures will also be referred to in the following description of the sections and signal flow among these sections of receiver 110 as presented in FIGS. 1-3. To facilitate understanding of the following description, receiver 110 sections shown on FIGS. 1-3 are generally set forth with initial letters capitalized in the following description, while discrete components and circuitry shown on FIGS. 4-39 are generally referred to below in lower case letters.

1. Teletext Group

In the teletext group (FIG. 1) of receiver 110 of the depicted embodiment, as shown in FIGS. 1, 2 and 3, System Control Section 111 controls or directs all functions of receiver 110. System Control Section 111 comprises, as shown in FIGS. 1 and 4-6, an Intel 8085A processor 113, an Intel 8257 direct memory access (DMA) controller 115, an 8K by eight bit read only memory (ROM) 117, a 2K by eight bit random access memory (RAM) 119, and Input/Output and Memory-Address Decoding Circuitry 121. A master clock signal is generated by 6 MHz Crystal Oscillator 118 (FIG. 30) and provided to the clock input pin of processor 113. This signal also passes through divider circuit 116 (FIG. 12) and is provided to Serial Interface Section 151 and Sensor Processing Section 213, discussed below.

The elements of System Control Section 111 are interconnected by a common bus 120 as described in the Intel 8085A microprocessor manufacturer's application notes, which are incorporated herein by reference. ROM 117 contains the machine language embodiment of the teletext or system control program, a listing of the source code for which is set forth below. In the present embodiment, these elements utilize the satellite signal to provide control signals to or receive and process control and video signals from the other portions of the teletext group (FIG. 1), the video group (FIG. 2) and the character generator group (FIG. 3) as described below.

Switch Input Section 123 comprises thirty-two switches 127 (FIG. 7), each of which provides a "0" or a "1" input into System Control Section 111. Twenty-one of these switches are for coding the proper address into receiver 110; three are for the time zone in which receiver 110 is to be used; three are for time offset hours and each of the remaining switches is for auxiliary time zone, time offset direction, remote weather sensor, radar enable, and test mode, respectively. In other embodiments, some or all of the switches may be used for other purposes. In groups of eight, as shown in FIG. 7, the switches 127 are connected to System Control Section 111 through buffers 129, which are addressed by processor 113 under software control.

System Control Section 111, acting through processor 113, controls LED Display Output Section 221, which comprises eight LED indicators 133 shown on FIG. 8 in the present embodiment. Six of the indicators 133 are activated by tri-state latches 137, which are controlled by processor 113. One indicator 133 is driven by the data-in signal 152 from Serial Interface Section 151, described below and shown in FIG. 4. The remaining indicator 133 is driven by the satellite video sense signal 252 from Gen Lock and Sync Generator Section 251, described below and shown in FIGS. 19-21. In the present embodiment, these indicators 133 indicate the following: addressing of the receiver, keyboard data being received, local television input selected for output, tape activation signal on, auxiliary audio on, teletext being received, local video being received and satellite video being received.

System Control Section 111, acting through processor 113, also controls Logic Output Section 139. Logic Output Section 139 comprises, as shown on FIG. 8, a tristate latch 143 controlled by processor 113, and the terminations of latch 143 outputs. Six of the eight latch 143 outputs are opto-isolated solid state switches 147, which ar terminated on the exterior of receiver 110 and which are utilized for control of external devices by the receiver 110 as follows: local commercial pre-roll for cueing local video programming, local commercial on-air, auxiliary audio on-air, weather warning for the weather warning mode of receiver 110 described below, radar for display of local radar information, and a spare. The seventh output 141 is an electromechanical relay 149 which may be terminated on the exterior of the receiver 110, for use in connection with the weather warning mode of receiver 110 to activate a cable station voice-over all channel capability. The eighth output of latch 143 is a video select signal which serves as an input to the Video Switcher Section 271 of the video group (FIG. 2) and the character generator group (FIG. 3).

Access by System Control Section 111 to external bi-directional EIA RS-232 compatible serial data communications is made possible by Serial Interface Section 151. In Section 151, as depicted in FIGS. 2 and 4, an 8250 universal synchronous asynchronous receiver transmitter (USART) 154 interfaces with the common bus 120 of System Control Section 111. This capability may be used for, inter alia, reception by receiver 110 of line signals from remotely located weather sensors.

DMA controller 115 of System Control Section 111 is provided access to satellite teletext information by Teletext Input Section 153, shown in FIGS. 1, 4 and 9-11. In section 153, teletext bit stream recovery circuitry 157, depicted in FIGS. 10 and 11, strips the teletext data from the satellite video signal input from Satellite Video Section 243 further described below. In the present embodiment, the satellite video signal containing 5.7272 MHz teletext data is amplified and fed to the composite video pin of a Signetics SAA 5030 teletext video processor 161. Video processor 161 samples this video and causes a high Q oscillator tank circuit 163 to become phase-locked to the teletext data. A separate one-shot 167, triggered by the leading edge of each video sync pulse in the satellite video signal, applies a signal to the Sandcastle input of the teletext video processor 161 for 11 microseconds. The components connected to the remaining pins of the teletext video processor 161 are in accordance with the manufacturer's application notes, which are incorporated herein by reference, and in the present embodiment such components are as depicted in FIGS. 10 and 11. The data and clock outputs of the teletext video processor 161 are fed to the Serial to Parallel Conversion Circuitry 171 in Synchronous Serial to Parallel Data Converter 173 (all circuitry on FIGS. 9-11 not including circuit 157).

In Serial to Parallel Conversion Circuitry 171, a multiplexer 177 (FIG. 10) selects one of three serial clock and data input sources. Typically, Teletext Bit Stream Recovery Circuitry 157 is selected; however, System Control Section 111 is selected when test mode switch 179 (FIG. 10) is in the test position, and in the event that one or more clock pulses are lost in the teletext data from Teletext Bit Stream Recovery Circuitry 157, a signal from Missing Clock Detector 181 causes the data input to be in the form of all zeroes and the clock input to be provided by System Control Section 111. The selected clock input is utilized to clock the selected data into an eight bit serial-in to parallel-out shift register 183, shown in FIG. 11. The parallel output of the serial-in to parallel-out shift register 183 is fed to Framing Detector 191 shown in FIGS. 9 and 11, and is also loaded into parallel data buffer 187 pursuant to a load signal from binary counter 189.

Binary counter 189 (FIG. 9) provides the load signal, upon receipt of an enable signal from Framing Detector 191, once every eight-bit times. The eight bit parallel teletext data from the serial-in to parallel-out shift register 183 thus passes through parallel data buffer 187 and is available for access on the common bus 120 by DMA controller 115 of System Control Section 111 on a first-in first-out basis, for storing in RAM 119 of System Control Section 111.

The eight bit parallel teletext data thus stored is accessed by processor 113 and fed under program control to Interprocessor Link Section 190, which provides an eight bit data path and a path for handshaking signals to Character Generator Control Section 313 discussed below.

Framing Detector 191 mentioned above operates on the framing byte of each teletext data line for synchronization purposes. A framing detector one-shot 193 enables this detector to use the parallel data from the Serial to Parallel Data Conversion Circuitry 171 to address framing ROM 197, shown in FIG. 11. Framing ROM 197 is encoded so that each location that corresponds to a valid framing character in a framing byte contains a zero and all other locations contain a one. The value fetched from the framing ROM 197 sets latch 199 when a framing character is detected. Latch 199 provides the enable signal mentioned above to Serial to Parallel Data Conversion Circuitry 171 and to Byte Counter 201. In this fashion, Serial to Parallel Data Conversion Circuitry 171 is synchronized with the boundary of the first byte of data in a teletext data line.

Byte Counter 201, shown in FIGS. 1 and 9, contains binary counters 203 that utilize the enable signal from latch 199 in Framing Detector 191 to ensure that exactly 34 bytes of data enter the parallel data buffer 187 of Serial to Parallel Conversion Circuitry 171 for each line of teletext. The output of Byte Counter 201 is provided to the reset input of latch 199 in Framing Detecter 191, which enables Serial to Parallel Conversion Circuitry 171 as described above.

Missing Clock Detector 181 mentioned above and shown in FIGS. 1 and 11 causes data input to Serial to Parallel Conversion Circuitry 171 to be in the form of all zeroes in the event that a clock pulse from Teletext Bit Stream Recovery Circuitry 157 is not sensed within 260 nanoseconds after the previous pulse. Missing Clock Detector 181 contains a one-shot 207 which is triggered by each clock pulse from Teletext Bit Stream Recovery Circuitry 157. If a clock pulse does not arrive within 260 nanoseconds after the previous pulse, the output of the one-shot 207 is terminated, thus setting missing clock latch 209, the output of which is routed to Serial to Parallel Conversion Circuitry 171.

Two other sections of the teletext group of receiver 110, in addition to Switch Input Section 123, Serial Interface Section 151 and Teletext Input Section 153, provide System Control Section 111 access to information. The first of these is Miscellaneous Data Section 211 (shown on FIGS. 1 and 14) which makes available on common bus 120 to System Control Section 111: (a) the status of the satellite video presence detector in the Gen Lock and Sync Generator Section 251, (b) the local video presence detector in Local Video Section 267, and (c) the position of the test mode switch in System Control Section 111. The second is Sensor Processing Section 213 (shown on FIGS. 1, 13 and 14) which processes inputs (shown on FIG. 13) from five externally connected weather sensor devices and makes their inputs available to System Control Section 111 on common bus 120. The weather input circuitry, shown on FIGS. 13 and 14, includes five circuits. Rain gauge processing circuitry processes signals from a rain gauge by conditioning and counting contact closures in the gauge. Wind velocity processing circuitry detects and counts the zero crossing of an alternating current input from a wind speed sensor. The three remaining processing circuits share an analog to digital converter 221 which is fed by three independent normalizing circuits. The first, a wind direction normalizing circuit, provides a signal to the analog to digital converter 221 that is proportional to the resistance of a variable resistance sensor element. The second, a humidity normalizing circuit, provides a voltage in the range of -200 to +200 millivolts that is proportional to the sensor input voltage to the analog to digital converter 221. The third, a temperature normalizing circuit, supplies a source voltage to a current regulating sensor and supplies a -200 to +300 microampere signal to the analog to digital converter 221 that is proportional to the current flow through the sensor. Sensor Processing Section 213 also includes precision voltage references 231 for the analog to digital converter 221 and for the three normalizing circuits.

The teletext of the receiver 110 also comprises an Audio Section shown in FIGS. 1 and 12, that is under the control of System Control Section 111. Audio Section 233 contains an analog multiplexer 237 that receives three independent audio inputs from external connections on receiver 110. Under control of System Control Section 111, one of these three inputs is selected to feed a unity gain audio amplifier 239. An additional function of Audio Section 233 is to produce an audio beep heard in connection with the weather warning feature of the receiver 110 which is described in Section C below. An oscillator 241 produces this beep, which is mixed with the selected audio signal, and which can be turned on and off under control of System Control Section 111.

2. Video Group

The second group of sections of receiver 110 is the video group, shown in block diagram form on FIG. 2 and in detail on FIGS. 15-28. Essentially, this group comprises video switching, keying and amplification circuits.

The satellite video signal, which may be from a conventional TVRO receiver, is input to Satellite Video Section 243 of receiver 110 shown in FIGS. 2 and 15 and 16. This Section comprises a conventional 6 dB amplifier and clamping circuit 247 shown in FIG. 15. The output of the amplifier and clamping circuit 247, amplified satellite video 248, is routed to Video Switcher Section 271, discussed below, for switching, amplification and eventual display; to Gen Lock and Sync Generator Section 251, also discussed below; to Teletext Bit Stream Recovery Circuitry 157 in the teletext group, for processing of the digital data in the vertical blanking interval; and to the sync stripper circuit 249 in this section 243 shown in FIG. 16. Sync stripper circuit 249 produces a normal 245 and an inverted composite 246 synchronization signal. The normal signal 245 is sent to Teletext Bit Stream Recovery Circuitry 157, Serial to Parallel Conversion Circuitry 171, and to Missing Clock Detector 181, all in the Synchronous Serial to Parallel Data Converter 173 discussed above in the teletext group. The inverted signal 246 is routed to the Gen Lock and Sync Generator Section 251.

Gen Lock and Sync Generator Section 251 of the video group shown in FIGS. 2, 15-16 and 19-22, and to which is input, inter alia, satellite video 248 from Satellite Video Section 243, provides National Television System Committee (NTSC) Standard timing signals to other sections of receiver 110. When an NTSC satellite video signal is supplied to this Section, these timing signals will be "Gen-Locked" or synchronized with that satellite video signal. This Section 251 contains a Fairchild 3262B television sync generator 253 that is coarsely synchronized to the satellite video signal 248 by comparison of the inverted composite or gen sync signal 246, supplied by Satellite Video Section 243 through digital delay networks 257, with the composite sync output of sync generator 253. Once coarse synchronization is achieved, as indicated by satellite video present signal 259 (which is routed to, inter alia. Miscellaneous Data Section 211 for input to System Control Section 111), the color burst from the satellite video signal 248 is applied to the reference input of an RCA CA 3126 burst lock chip 261 shown in FIG. 16. The phase locked burst frequency of this burst lock chip 261 passes through a multiply-by-four circuit 263 shown in FIG. 16 whose output is then used as the clock source for sync generator 253. The signals from this Gen Lock Section 251 are input to various circuits in the teletext, video and character generator groups of the receiver 110, as described below.

Local video signals are input to Local Video Section 267 of the video group of receiver 110 shown in FIG. 17. This section comprises a conventional 6 dB amplifier and clamping circuit 269 similar or identical to that in Satellite Video Section 243 mentioned above. The output of this amplifier and clamping circuit 269, a local video signal 270 similar to the video output of Satellite Video Section 243, is applied to Video Switcher Section 271 for switching, amplification and eventual display.

Video SWitcher Section 271 shown in FIG. 17, comprises a double pole analog solid state switch 273 which may be a Siliconix D6-191 and is controlled by video select signal 142 from Logic Output Section 139 of the teletext group. Switch 273 passes either the satellite video signal 248 from Satellite Video Section 243 or local video 270 from Local Video Section 267 to Background Keyer Section 277, discussed hereinbelow, for switching, amplification and eventual output for display.

Also applied to Background Keyer Section 277 is output 278 from Character Keyer Section 279 which section is shown in FIGS. 23-25. This Section 279 comprises a high speed video switch 281 (FIG. 25) capable of selecting either of two video input signals for output or rapidly keying between the two signals to produce an output consisting of elements from both input signals. The input signals to a first side of video switch 281 are background color video 290 from Background Generator Section 291 and internal composite sync 292 from Gen Lock and Sync Generator Section 251. The input to the other side of video switch 281 is the character picture element black/white control 294 from the Display Attribute Functions Section 427 of the character generator group (FIG. 3) after black and white level potentiometers 283 (FIG. 23) adjust to provide standard NTSC signal levels. The output 278 of switch 281 is passed through a transistor buffer 287 (FIG. 25) and feeds Background Keyer Section 277. Switch 281 is controlled by character data switch signal 295 from Display Attribute Functions Section 427 of the character generator group, and the composite blanking signal 296 from Gen Lock and Sync Generator Section 251. These two switching control signals 295 and 296 are gated in logic circuit 289 (FIG. 23) so that the input of the first side of switch 281 mentioned above is selected throughout the vertical blanking interval of the satellite video signal and during periods when there are no character picture elements.

Background Generator Section 291, shown in FIGS. 2 and 23-25, includes a ROM 293 (FIG. 23) which is addressed by the four bit color code signals CL0-CL3 372 from Display Attribute Buffer Section 371 of the character generator group. The value in each of the sixteen memory positions that can be addressed provides digital red, green and blue input bits to a National Semiconductor LM1886 TV video matrix D to A chip 297. Chip 297 is connected to a National Semiconducttor LM1889 video modulator 299 (FIG. 24) as shown in the manufacturer's application notes for video matrix D to A chip 297, which notes are included herein by reference. The color video signal from video modulator 299 is passed through a 4 dB chroma amplifier 301 (FIG. 25) to feed background color video signal 290 to Character Keyer Section 279. Background Generator Section 291 also provides a combined color burst and shaped internal composite sync signal 298 to Character Keyer Section 279. Internal composite sync signal 292 from Gen Lock and Sync Generator Section 251 is shaped by sine squared filter 303 and combined with a color burst from burst gate 307 (FIG. 24), whose inputs are the subcarrier signal and the burst gating signal from Gen Lock Sync Generator Section 251, to produce the composite sync signal 298.

As shown in FIG. 18, Background Keyer Section 277 receives either local or satellite video signals from Video Switcher Section 271 and character and background video 278 from Character Keyer Section 279. Background Keyer Section 277 comprises a high speed video switch 281 capable of selecting either of these two video signals for output, or rapidly keying between them to allow characters to be "titled over" the local or satellite video rather than a plain color background. Switching between the two sources is controlled by the character switch signals 295 from Display Attribute Functions Section 427 of the character generator group. The output of Background Keyer Section 277 is applied to Video Output Amplifier Section 311 (FIG. 18), which comprises a conventional video driver stage adjusted to provide a one volt peak-to-peak signal to the video output connector on the exterior of receiver 110.

3. Character Generator Group

The third group of sections of receiver 110 is the character generator group, shown in FIGS. 3 and 29-39. This group uses eight bit parallel teletext data received from the teletext group to generate signals which control, inter alia, Background Generator Section 291, Character Keyer Section 279 and Background Keyer Section 277 in the video group to produce teletext video signals for display.

This group is controlled by Character Generator Controller Section 313, which includes, in the present embodiment, an Intel 8085A processor 317, an Intel 8257 DMA Controller 319, and Input/Output and Memory Address Decoding Circuitry 321 (FIG. 28). These elements are interconnected by a secondary common bus 323 as found in the manufacturer's application notes for a common data bus for the 8085A processor 317, which are incorporated herein by reference, and as illustrated principally in FIGS. 29-30. A 6 MHz master clock signal is provided to processor 317 from the 6 MHz crystal oscillator 118 in System Control Section 111. Processor 317 inputs the eight bit parallel teletext data from Interprocessor Link Section 190 into RAM 329 in the Display and Programming Memory Section 327 of the character generator group, discussed below, and otherwise implements character display functions of receiver 110 by execution of the program in ROM 331 of Display and Program Memory Section 327.

Display and Programming Memory Section 327, shown in FIGS. 3 and 31-33, comprises RAM 329 having 20K byte capacity and ROM 331 having l6K byte capacity, which are on secondary common bus 323 (FIG. 32). RAM 329, as mentioned above, is used for storage of 8 bit parallel teletext (or text-page) data storage, and also for scratch-pad memory by Character Generator Controller Section 313. ROM 331 contains the program for processor 317 of Character Generator Controller Section 313, which program is discussed and listed below.

After initialization by processor 317, DMA controller 319 transfers the 8 bit parallel teletext data from RAM 329 to Display Attribute Buffer Section 371 and to Character Buffer Section 333, discussed below, of the character generator group.

Input-Output and Memory Address Decoding Circuitry 321 (FIG. 31) provides enable signals to the following Sections which communicate on secondary common bus 323: Display and Programming Memory Section 327, Interprocessor Link Section 190, and Keyboard Input Section 428 and Real Time Clock Section 429, discussed below.

Character Buffer Section 333 (FIGS. 34-36) receives eight bit parallel teletext character data in American Standard Code for Information Interchange (ASCII) form from DMA controller 319 and buffers this data in a pair of sixtyfour by four bit wide first-in first-out registers 337 (FIG. 36). The up to thirty-two bytes of data corresponding to a text line of characters or part of such a text line are initially loaded into registers 337 (FIG. 36) under control of DMA controller 319, and counters 341 (FIGS. 34 and 35). Since each row of characters occupies (in height) a plurality of scan lines of video, the bytes corresponding to a text line of characters are recirculated by multiplexers 339 out of and back into registers 337 for each scan line associated with that row of characters. For each such scan line, signal NOT-INH2 338 from Character Serializer Section 359 clocks the eight bit parallel teletext data out of registers 337, byte-by-byte and into Font Memory Section 353, each such byte determining which character, and in particular which sequential horizontal portion of that character, is displayed in that portion of the scan line.

To control the number of bytes loaded into registers 337, Display Attribute Buffer Section 371, described hereinbelow, sends WO and Wl width signals 340 to counters 341 in Character Buffer Section 333, which continuously presents to DMA controller 319 request signal DRQ2 343 until the corresponding DMA controller 379 acknowledgement signal NOT-DACK2 347 (FIG. 34) has been returned by DMA controller 319 enough times to satisfy the count. W0 and Wl width signals 340 are gated into counters 341 by a one-shot 349 controlled by NRD signal 351 from Display Attribute Buffer Section 371. Display Attribute Buffer Section 371 also clears registers 337 after data for the text line has been clocked out. Character Serializer Control Section 409, discussed below, provides recirculation clocking to registers 337 to sequentially recirculate by