A convolution arithmetic circuit has a multiplier/accumulator to multiply two digital data sequences and add up the products. The sequences are stored in memories which cycle at the same rates and with different scales. One memory containing the multiplicand data is periodically updated, while the other memory containing coefficient data has a storage capacity of about twice the previous memory.
Method and apparatus of error back-propagation for use in a neural network system. A first group (11) of processing devices (13.sub.1, 13.sub.2, 13.sub.3) performs the resolving steps and a second group (12) of analogous processing devices (13.sub.4, 13.sub.5) performs the training steps while backpropagating errors calculated in a central processing device (10). The synaptic coefficient matrix C.sub.ij of the first group and the transposed matrix T.sub.ji of the second group are simultaneously updated. This updating of the synaptic coefficients can be performed by means of multipliers (34.sub.1 to 34.sub.N) and adders (37.sub.1 to 37.sub.N).
A Finite Impulse Response (FIR) digital signal processing circuit uses a double-accumulator technique to drastically reduce the number of multiply-accumulate operations which are necessary per sample of input data. The amount of reduction is dependent upon the shape of the filter function to be convolved. A double-accumulator (D-A) can be implemented by first providing a set of D-A coefficients, which are derived from the filter coefficient stream (FCS). Each D-A coefficient is multiplied by a separate input data sample. The products are summed together along with the result of a previous multiplication of the same D-A coefficients with different input data samples. This first sum is added to another number to form a second sum. The other number is the previous value of the second sum. The second sum is the result. The derived D-A coefficients are fewer and simpler than that required by the conventional FIR implementation. Since multipliers are complex, costly, bulky and limited in speed, the D-A method can lessen these constraints.
An improved digital filter capable of advantageously completing a filter operation through a convolution using a filter coefficient used in each stage of multi-stage digital filters and previously stored in a ROM, which includes a control unit for outputting a control signal; an input buffer for buffering a data inputted in accordance with the control signal and for outputting the buffered data; a data storing unit for storing a data outputted from the input buffer in accordance with a control signal applied thereto; a ROM for storing a filter coefficient obtained through an operation of the filter coefficient of a multi-stage; an addressing unit for addressing an address of the filter coefficient stored in the ROM; and a multiplying and accumulating unit for convoluting the data outputted from the data storing unit and the ROM.
An interpolation filter is used in television standards conversion to decimate an input sequence of higher definition signals into an output sequence of lower definition signals. The filter is partitioned into a plurality of computational stages. Within each stage, the decimation coefficients are stored in a random access coefficient memory and applied to a multiplier to generate the product of a digital input signal and a stored coefficient. The RAM is operable in two modes: a first mode in which new sets of coefficients are serially input to the RAM during the field blanking period and a second mode in which different stored coefficients are output to the multiplier for consecutive digital signals to effect a non-integer decimation ratio.
A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.
