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Description  |
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TECHNICAL FIELD
This invention relates to a data communication network and, in particular,
to an interface having a data transmission flow control arrangement for
controlling the flow of data packets transmitted from a plurality of
associated data transmitting and receiving devices to the network.
BACKGROUND OF THE INVENTION
Data communication networks were popularized with the advent of electronic
computers and the development of digital signal processing techniques. A
typical data communication network is interconnected with a plurality of
data transmitting aand receiving devices by associated interfaces. The
data network typically comprises a bidirectional communication bus which
provides a medium for data transmission between the transmitting and
receiving devices. It is known to use packet-type data transmissions for
the communication network. The data transmitting and receiving devices
connected to the network or bus via an interface may comprise intelligent
or non-intelligent terminals, host computers, digital station sets and
personal computers. One or more devices may connect to a single interface,
and the interface connects to the communication bus. The interface
processes incoming and outgoing packet data transmissions to and from its
associated devices.
A problem with the above-described data network is that the network may be
subject to periods of high traffic since a number of transmitting and
receiving devices may be transmitting data packets concurrently. Several
schemes have been proposed to alleviate the traffic problem. One scheme
utilizes "windowing" arrangements to control the flow of data packets to
the network. In windowing, a transmitting device requests network access
via its interface to transmit a data message over the bus. A processor in
the interface responds to the request and determines the number of data
packets comprising the anticipated data message. The number of data
packets define the amount of interface buffer space required to serve the
data transmission session. This amount of buffer space is identified as a
"window". Following a determination of the window required to accommodate
the number of outstanding packets that may be extant, the processor scans
the buffer in the interface. If the buffer contains sufficient space to
accommodate the requested window, the processor allocates that amount of
space and then prompts the transmitting device to begin the session. The
processor stores the received packets in the allowed buffer space and then
transmits the stored packets over the bus. However, if the interface
buffer contains insufficient space to accommodate the requested window
size, the processor transmits an indication to the transmitting device to
abandon the request, and retry at a latter time.
A disadvantage of the above-described flow control arrangement is that such
an arrangement requires a substantial amount of interface processing time
to perform the required and complex flow control operations. Processing
time is utilized for the administration of the flow control function and
for the repeated retransmission requests. Following a first rejected
request, a transmitting device again requests network access to determine
when the buffer can again accommodate the requested window size.
Therefore, a transmitting device can generate several requests over a
period of time before buffer space actually becomes available. This
retransmission process wastes valuable processing time since each request
requires separate processing to determine buffer capacity. The use of a
substantial amount of processing time for repeated requests is not cost
effective and is an inefficient use of the processor resource with respect
to flow control operations.
SUMMARY OF THE INVENTION
To overcome the above-described problems and disadvantages, an interface
flow control arrangement for controlling the flow of data packets
transmitted from a plurality of data transmitting and receiving devices is
disclosed. This arrangement provides circuitry in the interface which
detects whether a buffer contains sufficient space to accommodate a data
packet of the maximum length that can possibly be received from an
associated device. When the buffer contains insufficient space to store a
packet of maximum length the interface includes specialized circuitry
which generates and applies a jam signal to all of its associated
transmitting and receiving data devices. The jam signal simulates the
conditions associated with a busy packet bus and inhibits the transmission
of data from any of the connected transmitting and receiving devices. The
interface terminates the application of the jam signal to all of its
associated devices when the buffer again contains sufficient space to
accommodate a data packet of maximum length. The disclosed flow control
arrangement stops data transmissions from all associated devices whenever
there is insufficient interface buffer capacity to store a data packet of
maximum length. Therefore, no data transmissions occur until such time as
sufficient buffer space is available to store a packet of maximum length.
As previously described, the typical packet network comprises a
bidirectional communication bus which interconnects a plurality of
interfaces where each interface connects to one or more data transmitting
and receiving devices. An interface comprises a processor for processing
incoming and outgoing data, a buffer for storing data packets, a selective
routing and transmission controller for administering the flow control
operation and a plurality of transmit/receive regulators for enabling and
disabling the jam signal. Each transmit/receive regulator is associated
with a transmitting and receiving device. The interface processor
continually monitors the buffer to detect available interface buffer
space. When the buffer contains sufficient space to accommodate a data
packet of maximum length, the processor receives data transmissions and
stores the received transmissions in the buffer.
Assume, now, that the buffer contains insufficient space to accommodate a
data packet of maximum length. The processor detects this condition, and
generates a control signal. The processor applies this control signal to
the selective routing and transmission controller. The controller
comprises a flow control register and a flow jam signal generator. In
response to the receipt of the control signal, the flow control register
generates a flow control signal. The flow control register applies the
flow control signal to the plurality of transmit/receive regulators. The
flow control register also applies the flow control signal to the flow jam
signal generator. The jam signal generator, in response to the flow
control signal, generates a jam signal and applies the jam signal to the
plurality of transmit/receive regulators. The transmit/receive regulators,
in response to the receipt of the flow control signal and the jam signal,
are enabled. The regulators extend the jam signal to each associated
transmitting and receiving devices. The jam signal inhibits the
transmission of any data from all the transmitting and receiving devices
served by the interface. The signal remains active until the buffer again
contains sufficient space to accommodate a data packet of maximum length.
In the above-described manner, the selective routing and transmission
controller and the transmit/receive regulators of the interface control
the flow of data to the communication bus.
An advantage of the disclosed flow control arrangement is that the flow
control function operates independent of continuous processor
intervention. When the processor determines that insufficient buffer space
exists, the controller and regulator administer the flow control operation
by generating and applying the jam signal to all data transmitting and
receiving devices associated with the interface. The jam signal
continually inhibits all data transmissions until sufficient buffer space
to accommodate a data packet of maximum length is available. This
continual inhibition eliminates the need for numerous retransmissions to
determine available buffer space. Since the disclosed arrangement does not
use a substantial amount of processing time to administer flow control
operations or to process retransmissions, the disclosed arrangement
provides for a number of economics and efficiencies over the prior art.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 discloses a data communications network architecture for packet data
transmissions;
FIG. 2 discloses the details of an interface of the network of FIG. 1;
FIG. 3 discloses the details of a selective routing and transmission
controller which comprises the interface of FIG. 2;
FIG. 4 discloses the details of a transmit/receive regulator which
comprises the interface of FIG. 2; and
FIGS. 5 and 6 discloses in flow-chart form the steps in the operation of
the flow control management arrangement.
DETAILED DESCRIPTION
FIG. 1 illustrates a typical architectural structure of a data
communication network. The network comprises a bidirectional master
communication bus 100, a plurality of data transmitting and receiving
(T/R) devices 110-0 through 110-n, 111-0 through 111-n, 112-0 through
112-n, 113-0 through 113-n and 114-0 through 114-n, and a plurality of
interfaces 104-0 through 104-n. Assume for the remainder of this
description that the data network serves to exchange data packets of
information between data transmitting and receiving devices. Data packet
transmission is known to the art and therefore, no further details are
provided.
Each data packet includes control information which controls the data
transmission, data information which comprises the actual data message,
and address information which identifies the origin and destination of the
data packet. The entire data packet is typically applied to and from the
interface of a destination transmitting and receiving device or an
originating transmitting and receiving device over a common bidirectional
bus which extends from the master communication bus to the interface.
However, for ease of description, each type of information has an
associated bidirectional bus such that control data is applied over
control buses 101-0 through 101-n, message data is applied over data buses
102-0 through 102-n, and address data is applied over address buses 103-0
through 103-n. The control, data, and address buses interconnect master
communication bus 100 to interfaces 104-0 through 104-n.
Interfaces 104-0 through 104-n process incoming and outgoing data packets
of information. The processes include formatting and unformatting data
packets, determining the originating and destination transmitting and
receiving device, routing data packets, extending data messages to and
from an originating and destination transmitting and receiving device, and
controlling access to and from master communication bus 100. The details
of the illustrated interfaces of FIG. 1 are discussed subsequently. Each
interface 104-0 through 104-n performs shared processing operations for a
plurality of associated connected transmittting and receiving devices.
Transmitting and receiving (T/R) devices 110-0 through 110-n, 111-0
through 111-n, 112-0 through 112-n, 113-0 through 113-n, and 114-0 through
114-n are connected to associated interfaces 104-0 through 104-n over
bidirectional paths 105-0 through 105-n, 106-0 through 106-n, 107-1
through 107-n, 108-0 through 108-n, and 109-0 through 109-n, respectively.
Data transmissions are received from and transmitted to interfaces 104-0
through 104-n over these bidirectional paths. The transmitting and
receiving (T/R) devices of FIG. 1 may be any type of data generating
devices such as a personal computers, intelligent or non-intelligent
terminals, host computers or digital station sets. For ease of
description, the transmitting and receiving (T/R) devices of FIG. 1 are
referred to as T/R devices.
FIG. 2 illustrates the details of one interface such as interface 104-0 of
FIG. 1. Interface 104-0 processes incoming and outgoing data transmissions
for a plurality of associated T/R devices 110-0 through 110-n as received
from or transmitted to master communication bus 100. Interface 104-0
comprises data processor 200, parallel to serial and serial to parallel
data converters 221 and 222, respectively, data packet buffer 201,
selective routing and transmission controller 203, transmit/receive
regulators 204-0 through 204-n and line transceivers 205-0 through 205-n.
Data processor 200 scans master communication bus 100 for data packets
over buses 101-0, 102-0 and 103-0, controls access to and from master
communicatioon bus 100 by detecting the busy/idle status of master
communication bus 100, formats and unformats outgoing and incoming data
packets of information, identifies the origin and destination of the
outgoing and incoming data transmissions, determines the start of and
termination of incoming and outgoing data transmissions and continually
monitors buffer 201 to detect the amount of available storage space. The
process of continually monitoring the buffer is discussed subsequently in
FIGS. 5 and 6. Processor 200 connects to data packet buffer 201 over
bidirectional path 212. Buffer 201 is typically a readable and writable
RAM-type memory. Buffer 201 stores a plurality of data packets to await
data processing by processor 200 prior to accessing master communication
bus 100. The scheme utilized by processor 200 to access the network is not
described since this scheme comprises no part of the disclosed invention
and is well known to the art.
Processor 200 connects to selective routing and transmission controller 203
over paths 220 and 207, and, indirectly, over paths 210 and 211 via
converters 221 and 222. Converter 221 connects to processor 200 over path
208 and performs parallel to serial data conversion on incoming data
transmissions; and converter 222 connects to processor 200 over path 209
and performs serial to parallel data conversion of outgoing data
transmissions. Converters of the above-described type are known to the art
and are, therefore, not described in further detail. Converters 221 and
222 connect to controller 203 over paths 210 and 211, respectively.
Controller 203 and regulators 204-0 through 204-n comprise the hardware for
the disclosed subject invention. Controller 203 and regulators 204-0
through 204-n control the data transmission flow from T/R devices 110-0
through 110-n by jamming all T/R devices 110-0 through 110-n when buffer
201 cannot store or accommodate a data packet of maximum length. The
details of controller 203 are described subsequently. Controller 203
connects to transmit/receive regulators 204-0 through 204-n over paths
214-0 through 214-n, 215-0 through 215-n, and 216-0 through 216-n. Each
transmit/receive regulator 204-0 through 204-n is associated with a T/R
device 110-0 through 110-n. Transmit/receive regulators 204-0 through
204-n comprise the logic to regulate the transmission of data to and from
the associated T/R devices 110-0 through 110-n. Further details of
transmit/receive regulators 204-0 through 204-n are discussed
subsequently.
Each transmit/receive regulator 204-0 through 204-n connects to an
associated line transceiver 205-0 through 205-n over paths 218-0 through
218-n and 219-0 through 219-n, respectively. Line transceivers 205-0
through 205-n drive incoming and outgoing data transmissions along the
appropriate data transmission path to either an associated destination T/R
device or to the associated regulator. Line transceivers are known to the
art and therefore, no further detail is provided.
The above description identifies each element of the interface and
describes, in general, the purpose of each element within the interface.
The following description describes the functions and operations of the
elements only with respect to an outgoing data transmission. The
operations of the interface with respect to incoming data transmissions
are not relevant to the discussion and the purpose of this invention.
Therefore, the remainder of this description discusses only outgoing data
transmission from any one or more T/R devices 110-0 through 110-n to
master communication bus 100.
Assume that one or more T/R devices 110-0 through 110-n are transmitting
data to access the network. For ease of description, only one T/R device,
110-0, is discussed; however, the other T/R devices 110-1 through 110-n
operate in the same manner. Assume further that buffer 201 has sufficient
space to accommodate a data packet of maximum length. T/R device 110-0
applies data to line transceiver 205-0 over lead 105-0. Line transceiver
205-0 applies the outgoing data transmission to regulator 204-0 over XMIT
path 219-0. Regulator 204-0 applies the outgoing data transmission to
controller 203 over path 216-0. Regulator 204-0, concurrently, applies an
activity signal to selective routing and transmission controller 203 over
path 215-0. The activity signal indicates that a T/R device is actively
transmitting data. Controller 203 responds to the receipt of the activity
signal on path 215-0 and the data on path 216-0 by concurrently executing
the following operations.
Controller 203 applies the generated data to converter 222 over path 211.
Converter 222 converts the data from a serial data stream to a parallel
data configuration and applies the parallel data to processor 200 over
path 209. Assume now that processor 200 cannot currently access master
communication bus 100. Processor 200 applies the received data
transmission over path 212 to buffer 201. Processor 200 scans master
communication bus 100 to detect the busy/idle status of the bus. When
processor 200 detects that master communication bus 100 is idle, processor
200 retrieves from buffer 201 over path 212 the transmitted data packet
and applies the packet to master communication bus 100 over control path
101-0, data path 102-0 and address path 103-0. The processes by which
processor 200 detects an idle status on bus 100 is not described since
that process does not comprise any portion of the subject invention and is
well known to the art. Controller 203 also "echoes back" the outgoing data
transmission to the T/R device, 110-0, originating the data transmission.
Controller 203 "echoes back" the outgoing data transmission to all T/R
devices 110-0 through 110-1 by processing the outgoing data transmission
through the data merger function which provides a common data transmission
path for all data transmissions. This process is discussed subsequently in
connection with FIG. 3. However, the remaining discussion is with respect
to T/R device 110-0. The "echo back" data is an error checking function to
confirm the accuracy of the data transmission. Controller 203 applies the
"echo-data" to transmit/receive regulator 204-0 over path 216-0.
Transmit/receive regulator 204-0 applies the "echo-data" to line
transceiver 205-0 over receive path 218-0. Line transceiver 205-0 applies
the "echo-data" to T/R device 110-0 over transmission path 105-0.
At the conclusion of a data transmission by T/R device 110-0, no data
appears on path 216-0 and an inactive activity signal exists on path
215-0. Controller 203 responds to the lack of data on path 216-0 and the
absence of the activity signal on path 215-0 and generates an active End
of Transmission (EOT) signal to indicate a termination of the data
transmission. Controller 203 applies the active EOT signal to processor
200 over path 207. Processor 200 detects the termination of the data
transmission in response to the receipt of the active EOT signal. The
details of the EOT signal with respect to processor 200 are discussed
subsequently.
The above description discusses the function of the elements of the
interface with respect to an outgoing data transmission from one of the
T/R devices of the interface. Assume now that multiple T/R devices such as
110-0 through 110-n are concurrently transmitting data. Data is applied to
line transceivers 205-0 through 205-n and regulators 204-0 through 204-n
in the manner previously described. In response to multiple transmissions,
regulators 204-0 through 204-n each generate activity signals indicating
data transmission activity. Regulators 204-0 through 204-n apply the
activity signals to controller 203 over associated paths 215-0 through
215-n. Regulators 204-0 through 204-n apply the data transmissions to
controller 203 over associated data paths 216-0 through 216-n. Controller
203 merges the incoming data transmissions on paths 216-0 through 216-n to
generate a single convoluted data output over path 211. The process of
merging data is discussed subsequently in FIG. 3. Controller 203 extends
the convoluted data to processor 200 over path 209. However, processor 200
ignores the received convoluted data since processor 200 cannot process
intermixed data messages. Processor 200 only process a single data
transmission at one time. Controller 203, as previously described,
"echoes-back" the data transmission. However, since several data
transmissions are merged into a single convoluted data stream, controller
203 applies the convoluted data transmission to all associated T/R devices
110-0 through 110-n over data paths 216-0 through 216-n. Regulators 204-0
through 204-n extend the convoluted data resulting from multiple
transmission activity to all T/R devices 110-0 through 110-n over paths
105-0 through 105-n. In response to a receipt of the convoluted data on
paths 105-0 through 105-n, all T/R devices 110-0 through 110-n stop
transmitting because of the receipt of convoluted data indicating multiple
activity. Only a single data transmission can be processed at a time, and
therefore any multiple data transmission activity precludes proper data
processing operations.
The above-description discusses both a single data transmission from one
T/R device and multiple data transmissions occurring simultaneously from
multiple T/R devices. In both cases, buffer 201 had sufficient space to
accommodate a data packet of maximum length. Now, assume that buffer 201
does not have sufficient space to accommodate any further transmitted data
packets of maximum length, and that no data transmissions are currently
occurring. The EOT signal on path 207 is active to indicate no data
transmission activity is present. The process of detecting sufficient
space in buffer 201 is discussed in connection with FIGS. 5 and 6.
In response to the detection of insufficient buffer space in buffer 201,
processor 200 generates a control signal to controller 204 over path 220.
Controller 203, discussed in detail subsequently, generates a regulator
control signal. Controller 203 applies the regulator control signal to
regulators 204-0 through 204-n over paths 214-0 through 214-n. Regulators
204-0 through 204-n extend the regulator control signal through
transceivers 205-0 through 205-n to T/R devices 110-0 through 110-n over
paths 105-0 through 105-n. The regulator control signal jams T/R devices
110-0 through 110-n so that no data transmissions can occur while the
regulator control signal is active. The regulator control signal remains
active until such time as processor 200 detects that buffer 201 can
accommodate a data packet of maximum length. Following the detection of
adequate buffer space, processor 200 terminates the control signal on path
220 which deactivates the regulator control signal on paths 214-0 through
214-n. In response to the termination of the regulator control signal,
normal data transmissions from T/R devices 110-0 through 110-n are
extended to processor 200.
FIG. 3 illustrates the circuit details of selective routing and
transmission controller 203 which comprises interface 104-0. Controller
203 comprises data merger 311, 1/N EOT activity detector 304, flow control
register 312, and flow jam signal generator 313.
The following describes the operations and functions of the elements of
controller 203 with respect to an outgoing data transmission from one T/R
device such as T/R device 110-0. Assume further that buffer 201 has
sufficient space to accommodate a maximum length data packet. Data
generated from T/R device 110-0 is received by controller 203 over data
path 216-0. Data 216-0 applies the generated data transmission to data
merger 311 over XMIT path 302-0. Data 216-0 comprises XMIT data 302-0 and
data 211 paths. For ease of description, however, only a single
bidirectional path 216-0 is shown as connected to controller 203. Data
merger 311 extends the transmitted data through multi-input AND gate 303.
AND gate 303 extends the transmitted data to data path 211. Controller 203
extends the data to processor 200 on path 211 in the manner and for the
processing operations previously described. As previously discussed,
controller 203 extends "echo-data" to each T/R device 110-0 through 110-n
over paths 216-0 through 216-n. The "echo-data" is a result of the ANDing
function of multi-input AND gate 303. The output of AND gate 303 is a
single bidirectional data transmission path, Data 211, where the
transmitted data is extended to both processor 200 and T/R devices 110-0
through 110-n. In particular, controller 203 applies the "echo-data" on
data path 211 over data paths 216-0 through 216-n. All regulators 204-0
through 204-n receive "echo-data" over data paths 216-0 through 216-n.
Regulators 204-0 through 204-n extend the "echo-data" to T/R devices 110-0
through 110-n. As previously described the "echo-data" performs an error
checking function to determine the accuracy of the data transmission.
T/R device 110/0, as previously described, also generates an activity
signal indicative of data transmission activity. The activity signal on
path 215-0 is applied to 1/N EOT detector 304. In response to the receipt
of the activity signal, detector 304 generates an inactive EOT signal to
indicate that a data transmission is currently in progress. Detector 304
applies the inactive EOT signal to processor 200. The inactive EOT signal
indicates to processor 200 that a data transmission is presently
occurring. If more than one T/R device 110-0 through 110-n is concurrently
transmitting data, for example, data merger 311 receives data inputs over
paths 302-0 through 302-n. AND gate 303 merges all incoming data
transmissions and generates "convoluted" data over path 211, as previously
described. When concurrent multiple data transmissions occur, detector 304
receives activity signals over paths 215-0 through 215-n. Detector 304
generates an inactive EOT signal which indicates data transmission
activity. If no transmission activity is present, an active EOT signal is
applied from detector 304 to processor 200 over path 207. An active EOT
signal indicates that no data transmission(s) are currently occurring.
Assume, now, that following the conclusion of the above-described data
transmission as indicated by an active EOT signal on path 207, processor
200 detects that buffer 201 can no longer accommodate a maximum size data
packet. The process of determining available buffer space is discussed
with respect to FIGS. 5 and 6. In response to this detection, processor
200 generates a control signal to controller 203 over path 220. The
control signal is essentially an on/off type signal which when active
turns on flow control register 312. In response to the active control
signal on path 220, flow control register 312 generates a flow signal.
Register 312 applies the flow signal to regulators 204-0 through 204-n
over path 314 and to flow jam signal generator 313 over path 314.
Generator 313 generates a jam signal in response to the receipt of the
flow signal on path 314. The generated jam signal may conform to the
CSMA/CD standards set forth by the IEEE Task Force 802.3 in the IEEE Draft
C, October 1985 paper entitled "Physical Signalling, Medium Attachment,
and Baseband Medium Specification Type IBASE5". Generator 313 applies a
jam signal to regulator 204-0 through 204-n over path 315. Both signals,
jam and flow, are applied over regulator control paths 214-0 through
214-n. Regulators 204-0 through 204-n, as previously described, extends
the control signal comprising the jam and flow signal to T/R devices 110-0
through 110-n. This signal prevents T/R devices 110-0 through 110-n from
generating any data transmissions. This arrangement prevents processor 200
from receiving overflow data. Since at this time, the buffer, 201 cannot
accommodate a data packet of maximum length. When the data buffer can
again accommodate a data packet of maximum length, processor 200 "turns
off" the control signal on path 220 which in turn turns off flow control
register 312. In response to the lack of an active control signal,
register 312 stops generating a flow signal over path 314. In response to
the lack of an active flow signal, generator 313 stops generating a jam
signal over path 315. The inactivity of the flow and jam signal prevent an
active signal on regulator control paths 214-0 | | |
