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BACKGROUND OF THE INVENTION
This invention relates to medical electronics in general, and more
particularly to an improved digital x-ray image processing system, that
utilizes the visual output of an image intensifier, designated fluroscope,
for generating an analog video input signal which is subsequently
digitized and manipulated in the digital domain and, finally, reconverted
to analog video for review in real time or digitally stored for post
examination by physician, diagnostician.
The use of fluoroscopy in medical dignostic procedures through which
invisible x-rays are directed through a patient and converted into visual
images by an image intensifier tube, (fluroscope) which images, through
the inclusion of optics, are directed into video or film containing
mechanisms, is well known in prior art. A good explanation of the manner
in which such is used in the prior art is described in U.S. Pat. No.
4,193,089. While this analog video image permits and examination of the
results in real time, the analog film images require subsequent chemical
processing and, therefore, are used later for more detailed diagnosis.
Digital x-ray or digital radiography utilizes the basic components of
fluroscopy up to and including the image intensifier and analog video
which is converted into the digital domain for computer manipulation that
enhance the basic signal information and allow a series of algorithms to
be applied in various real time or post processing steps, determined by
the examining physician.
Angiography, the x-ray examination of the major blood vessels using
contrast agents, is utilized when a patient is suspected by a physician of
having some form of cardiovascular or arteriosclerotic disease. Among the
most common procedures are the coronary arteries which supply blood to the
heart muscle, the carotids which are the major arteries in the neck
providing blood to the brain, the cerebral arteries themselves and the
renal arteries which provide blood to the kidneys. The arteries are common
sites of arteriosclerosis which, if properly diagnosed, can be treated
surgically or with drugs. Conventional x-ray angiography requires a
surgical procedure to permit the insertion of as catheter and injection of
contrast media directly into the artery to be examined. This procedure is
uncomfortable for the patient, involves a degree of risk and requires
hospitalization for three days. Therefore, only highly symptomatic
patients are referred for such procedures. Digital subtraction angiography
(DSA) permits contrast media to be injected interavenously in certain
procedures rather than by arterial catheterization, so that the procedure
can be done on an outpatient basis. The computer memory records and x-ray
image of the area of the body under study and then subtracts this
information from a second x-ray image taken after injection of the
contrast media, thereby eliminating anatomical structures. Attempts to
record coronary artery information with intravenous contrast injections
has yet to prove successful. Limited digital recording media and limited
transfer rates to digital media has further limited the usefulness of
digital techniques in studying the coronary arteries.
There is, thus, a need for an improved fluoroscopy system which permits
viewing and recording of fluoroscopic images, in real time via a video
display, as a radio-opaque material is injected into or ingested by a
patient and the patient irradiated with X-rays, which has sufficient
contrast at the time to permit the physician to be assured that the
procedure was successful and does not have to be repeated. Furthermore,
there is a need to be able to store responses and re-study these
television images instead of or in conjunction with film images at a later
time.
SUMMARY OF THE INVENTION
The present invention provides such a system. Analog image information
generated by a camera which may be an interlaced or progressive scan video
camera viewing a fluorographic image, is digitized and supplied to an
image enhancement system. The image enhancement system operates under
control of a host computer receiving inputs from an interactive terminal
with keybord, voice, or light pen inputs. The digitized image is also
perferably recorded on a wide-band tape recorder. The output image is
provided to a black-and-white monitor. Image information can also be
provided, after off-line processing and enhancement, to a color monitor.
Preferably, the host computer is equipped with an modem to permit remote
transmission of the information for analysis to and from remote locations,
if desired.
The system described herein uses a high speed, high density digital
recording media that permits full bandwidth capture of
512.times.512.times.10 bit digital data stream.
The composite elements of the system including a real time 2-D filter, a
multiplicity of image buffers and the frame processors and the real time
high density digital storage media are intended to permit examination
procedures of the coronary arteries in a less invasive, less costly, less
time consuming manner.
Whereas present film techniques of coronary arteries require the catheter
to be inserted directly into the artery selected for examination and the
radio-opaque dye injected directly into the artery to obtain sufficient
contrast in the resultant film image, digital techniques with inherently
greater contrast detectability characteristics can allow an examination
procedure to be conducted by placing a catheter in the region of the
origin of the coronary artery and still provide sufficient contrast
detectability even with the dilution of dye by the blood.
The filtering, transfer and reconstruction and recording of the entire
process is obtained at thirty images per second thereby permitting the
results of the examination to be reviewed in real time as well as post
examination with the uncontaminated, pure digital data base that was
recorded as the procedure was conducted.
The image enhancement system is the essential part of the system which
permits generating an enhanced image which gives the system its advantages
over the prior art permitting carrying out diagnostic procedures with
dilute levels of radio opaque material. This, in turn permits
catheterization which is less invasive to the specific coronary artery,
substantially reducing the risks involved, for example, in obtaining a
coronary angiogram.
Digitized information is operated upon in a plurality of frame processor
modules and in the two demensional (2-D) filter. Various combinations of
frame processing and filtering are available to carry out different types
of image processing. For example, conversion between interlaced and
noninterlaced formats is carried out when required, in three frame
processors (one to deinterlace and two to re-interlace). Other frame
processors provides arithmetic logic for mask processing. One frame
processor is simply used for image storage for downloading.
An important part of the image enhancement system is the 2-D filter. This
filter is of the general nature described in the article "Real Time Signal
Processing With Two-Dimensional Filters" by Jones et al., from the
Proceedings of the Society of Photo-Optical Instrumentation Engineers,
Volume 156, Modern Utilization of Infrared Technology, IV (1978), pp.
43-48. The 2-D filter is a filter which carries out a two-dimensional
convoltion utilizing a scanning kernal in order to intensify differences
between boundaries which are close on the grey scale to enhance these
edges. The filter, thus, for example, enhances the boundary between a dye
within the lumen of an artery and the artery wall. The physician carrying
out the diagnosis, because of this enhancement, can immediately see
whether the procedure is being effective and, if necessary, re-run it.
Perferably, a wide-band tape recorder is associated with the system. Stored
on the wide-band tape recorder is the digitized information from the
digitizer before processing. The use of such a wide-band tape recorder
permits storing this information in real time and reprocessing it as many
times as necessary under different conditions at a later time to carry out
more detailed diagnosis. Thus, a particular configuration of the image
enhancement system during the diagnosis procedure does not fix the
recorded image. The recorded image can be played back through the system
under many different configurations, each of which can provide different
types of enhancement to aid in diagnosis.
Furthermore, header information identifying the patient and all conditions
during diagnosis is also be recorded on the wide hand tape recorder for
identificatin and searching purposes.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the overall system of the present invention.
FIG. 2 is a more detailed block diagram of the real time of processor
portion of the system of FIG. 1 showing interconnecting buses.
FIG. 3 is a diagram helpful in understanding how an interlaced picture with
a four to three aspect ratio is converted into a square array of
digitialized pixels.
FIG. 4 is a block diagram of the digitizer of the present invention.
FIG. 5 is a block diagram of the digitizer interface of the present
invention.
FIG. 6 is a block diagram of the frame processor of the present invention.
FIG. 7 is a block diagram illustrating in more detail some of the address
logic of the frame processor of FIG. 6.
FIG. 8 is a block diagram of the wide-band tape interface of the present
invention.
FIG. 9 is a schematic presentation of the manner in which data is recorded
on a wideband tape recorder.
FIG. 10 illustrates in more detail the packing of a group of 13 pixels into
ten 13 bit words.
FIG. 11 shows in more detail the manner in which the programmable logic
array breaks up the first, fifth and ninth words and adds them on to the
10 bit words of the remaining ones of a group of 13.
FIG. 12 is an overall block diagram of the 2D filter utilized in the system
of the present invention.
FIG. 13 is a more detailed block diagram of the 2D filter of FIG. 7.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is an overall block diagram of the system of the present invention.
An X-ray generator 7 passes x-rays through a patient 9 on a table 8. The
radiation passing through patient 9 is imaged on an image intensifer 10
which converts the x-ray radiation into a visible image. As illustrated,
either an interlaced camera 11 or progressive scan camera 13 may be used
to view the image. One of the camera outputs is coupled through a switch
15 into a digitizer 17 within a real time processor 19.
The real time processor includes, in addition to the digitizer 17, an image
enhancement system 21 with which there is associated a 2-D filter 23. One
output from the image enhancement system is provided to a black-and-white
monitor 25. Another output is provided to a wide band tape recorder 27.
The image enhancement system is under the control of a host computer 29 in
an off-line analysis and measurement system 31. Associated with the host
computer is a computer tape drive 33 and disc drive 34. Also provided,
coupled to the host computer 29, is a modem 35 permitting communication
with remote locations. The host computer 29 receives inputs from an
operator control 37 which includes an interactive terminal 39 having a
voice input 41 and a light pen input 43. In addition to the outputs
provided to control the image processing, outputs are provided to a video
processor 44 and color monitor 45 in a video display unit 47 used in
off-line processing with the image enhancement system. The computer 29
also controls x-ray generator 7 through a programmable system interface
30. To provide additional control over the video processor and color
monitor a joystick 49 is provided.
FIG. 2 is a more detailed block diagram of the image enhancement system
showing its various interconnections. The output of the camera 11 or 13 is
provided as an input to digitizer 17. The output of digitizer 17 on a bus
101 is an input the digitizer interface and composite video generator 103.
The digitizer interface has two outputs. A bus 107 is provided as an input
to a de-interlace frame processor 111. A line 109 containing processed
analog video information is coupled to monitor 25.
The output of the de-interlaced frame processor, which is used to
deinterlace an interlaced input, is provided as an input to a first
arithmetic and logic unit (ALU) frame processor 113 over bus 107. The
manner in which this is accomplished is disclosed in detail in U.S. Pat.
No. 4,532,546 entitled Real Time Single Frame Memory For Converting Video
Interlaced Formats filed on even date herewith and assigned to the same
assignee as the present invention. The output of this first frame
processor 113 is provided on a bus 115 to a second frame processor 117.
Frame processor 117 can also receive an input directly from frame
processor 111, bypassing frame processor 113 over the "A" bus 114. This
bus also connects to frame processor 111 and with other units to be
described below. The output of frame processor 117 is provided on bus 119
which is coupled into the 2-D filter 23. The 2-D filter 23 can also
receive an input from the "A" bus 114. The 2-D filter recieves
instructions from the LSI-11 through a DRV11J parallel programable I/O
port. The output of the 2-D filter is on a bus 121 which is provided as an
input to a display frame processor 122, which provides its output on bus
124 to an interlace frame processor 123. Interlace frame processor 123
works with a further frame processor 125, to which it is coupled by bus
126, used as an interlace buffer to re-interlace the signal. All of these
frame processors can also receive an input from the bus 114.
Display frame processor 122 is used for storage and downloading. The
interlace frame processors 123 and 125 put the deinterlaced digitized
information back into an interlaced format from which it is coupled via
bus 128 to digitizer interface 103, which contains a composite video
generator, which converts the digital information into an analog video
signal which can then be displayed on the black and white monitor 25. Each
of the various frame processors is also coupled to the "B" bus 127A or
127B. Furthermore, a direct memory access or DMA bus 133 via a DMA
inteface 135, provides direct access to the memory associated with host
computer 29 of FIG. 1. DMA interface 135 is also coupled to each of the
other units over the DA bus 137. Information to and from the host is via
bus 139 and LSI-11 29a. It is on this bus that commands for each of the
frame processors, the 2-D filter, the digitizer and wideband tape
interface 131 are provided to set up the system configuration, as
described below.
The digital image is digitized into an array of 512 by 512 pixels. Each
pixel is represented by 10 bits. The frame processors are capable of
performing the functions of read, write, add, subtract, negate, exclusive
or, and intensity transformation. These functions are utilized to carry
out the interlacing and deinterlacing mentioned above, to do mask
subtraction, display buffering, perform arithmetic logic and carry out
incremental subtraction etc. The direct memory access permits the host
processor 29 to control the individual frame processors and 2-D filter.
The data transfer rate over this bus is approximately 500,000 words per
second (in bursts).
Preferably, the wide-band tape recorder 27 is a Honeywell HD-96 or
equivalent. Real time data can be stored into this recorder at rates of 1,
2, 3, 4.28, 5, 6, 7.5, 12 and 30 frames per second.
The recorder is capable of playing back at variable speeds through the
interface from 1 to 30 frames per second. The maximum transfer rate is
83.3 megabits per second, allowing approximately 7.5 minutes of data at 30
frames per second or 3.7.times.10.sup.10 usable bits to be recorded per
reel. Data is recorded and played back using an NRZ-L code. The wideband
tape recorder interface 131 permits the control of the wide-band recorder
by the host computer including annotation. Frame identification characters
and frame counts are added to allow search and knowledge of the real time
processor configuration when the data was recorded. However, as noted
above, only unprocessed data is stored.
The video display system 47 of FIG. 1 is, for example, a commercially
available DEANZA I.D. 5512 with color display. This is used to provide
pseudo-color, grey scale thresholding, gray scale expansion, contrast
enhancement, histogram generation and alpha-numeric display. Included is
an image intensity transformation memory (ITT). In conjunction with the
joystick 49 of FIG. 1 it is also used to provide linear and area
measurements. It is equipped with a LSI-11 DMA card to permit it to
interface with the LSI-11/23 computer through a Q bus converter located in
the LSI 11/23 back plane. Thus, the host computer 29 is preferably a DEC
LSI 11/23 CPU with 256K bytes of random access memory, 4 serial EIA lines,
1 Q-verter, a 500 KHz DMA card, 1 DRV11-J parallel I/O card 118, and a DSD
880 floppy/Winchester system 34 and interface. The tape drive 33 is
preferably a 9 track computer compatible tape recorder and interface
operable at 1600 BPI and 125 IPS.
The operator controls 37 will preferably include an ISC 800 IG color
terminal 39 with light pen 43, keyboard and voice input control 41.
Included will be a programmable system interface to permit controlling and
monitoring of the external systems consisting of a general purpose DEC I/O
board with a software driver.
THE INTERLACE AND NON INTERLACE FORMATS
The interlaced configuration in a standard television camer has an aspect
ratio of 4:3. That is to say it is 4 units wide and 3 units high. The
sequential camera on the other hand normally has a 1:1 aspect ratio, i.e.,
it produces a square picture. It is desirable to process square pictures
and square pixels in the image. Furthermore, the image intensifier tube is
generally circular, and in any case does not have an aspect ratio of 4:3.
Thus, even if a conventional television camera with interlaced scan and
4:3 aspect ratio views an image intensifer the image is contained within a
square. The system of the present invention is set up to operate on an
array of 512 by 512 square pixels each represented by 10 bits of
information.
As illustrated by FIG. 3, if one considers a line of pixels on a television
raster with a 4:3 aspect ratio and 512 lines of vertical resolution, if
square pixels are to be generated, across each line there will be
approximately 4/3 times 512 or 682 pixels. The image information will be
contained within the 512 pixels in each line in the center of the screen
on which the circular image intensifier image 91 is located. Thus, in
processing the image, when it is obtained from a conventional interlaced
camera, there should be a delay at the beginning and end of each
horizontal scan. For example, as indicated by FIG. 3 conversion should
start only when, e.g., pixel 85 is reached and continue for 511 additional
pixels to pixel 596. The manner in which this delay is implemented will be
seen below. This then gives the 512 by 512 array of square pixels.
Similar delays have to be introduced when converting the image back into
analog format i.e. only in the area between pixel 86 and pixel 597 should
video information be provided on the output from the digitizer interface.
The system of the present invention is based on operating at a basic
horizontal frequency of 10 MHZ. That is to say, assuming a square
sequential scan input, information is converted at a pixel rate of 10 MHZ.
There is a certain amount of time allotted for scanning across a line and
converting 512 pixels at this rate, plus a time for retrace. When scanning
a tube having a 4:3 aspect ratio as in FIG. 3, one and one-third as many
pixels must be scanned in this time. Thus it is necessary to accelerate
the rate of data conversion by four-thirds in order to scan the 512 pixels
in the center portion of the screen within the allotted time. For this
reason, at the input, and again at the output, a 13 MHZ clock accelerator
is provided to carry out the necessary acceleration for the 4:3 aspect
ratio of the input and the display output.
Finally, it is difficult with presently available hardware to carry out
frame processing in the frame processors at 10 MHZ. Since there is, in a
scanning corresponding to a conversion at 10 MHZ, a considerable amount of
time utilized in retrace, it becomes possible to utilize this time for
computation within the frame processors, and, thus, information is
operated on continuously in the frame processors at a frequency of 8.33
MHZ. While, this operation is continuous, lines of information are read in
to the system in bursts, with gaps in between to take into account
retrace.
On the different buses throughout this system, in additional to the digital
information being transferred, there is also timing. The basic elements in
timing are the line frequency or a line sync signal and the frame
frequency or a frame sync signal, in addition to the system clock at 8.33
MHZ or 10 MHZ.
DIGITIZER AND INTERFACE
The basic purpose of the digitizer and digitizer interface is to take
information in analog format from a television camera or to take
information from another source or a test pattern and get into a form in
which it can be processed by the frame processors, i.e., to get it at the
proper frequency and with the proper synchronization signals. In addition,
the other end of the digitizer interface system takes the processed data
which is being input to the digitizer at the system frequency of 8.33 MHZ
and converts it into the necessary output frequency of 13 MHZ to display
on the conventional T.V. display which has a 4:3 aspect ratio.
FIG. 4 is a block diagram of the digitizer. At the heart of the digitizer
is an analog-to-digital converter 201 receiving a video input on line 203
from either an interlaced camera or a sequential scan camera. An input on
line 205 is an encode command to the converter and an output on line 207 a
data-ready output. A data output of 10 bits of data is provided on a data
bus 209. The converter may be an Analog Devices Model 1020 for example. In
addition to converting the video information, the digitizer also includes
a sync recovery circuit. The video signal, assuming that an interlaced
scan with composite sync in the video signal is provided, is coupled into
a sync recovery circuit 211 of conventional design where the sync is
separated out from the video to provide a composite sync signal on line
213. This composite sync signal is coupled to a pulse shaping and
regeneration circuit 215 made up, primarily, of a group of monostable
multivibrators from which three signals are provided as outputs. The first
is the composite sync in line 218 which will include both a vertical and
horizontal sync information, a signal labeled CFS on line 219 which is the
frame sync and a signal designated CN on line 217 which is a short pulse
ocurring at the field-time, i.e, occurring at the division between odd and
even fields. Each of lines 217-219 is provided to an AND gate 220.
As indicated above, the system must also work with a sequential scan
camera. Such a camera provides as outputs a frame sync signal which is an
input on line 221, a line sync signal which is an input on line 223 and a
frame index signal which is an input on line 225. Lines 221 and 223 are
clamped by zener diodes 227 and 229, respectively. Each of the three lines
is coupled into a line receiver and driver 231 having uninverted and
inverted outputs.
To select between either the recovered sync from the pulse shaping and
regeneration circuit in the case of interlaced scan or incoming signals on
lines 221, 223 and 225 in the case of sequential scan, a multiplexer 233
is provided. The inverted index signal and the inverted CIN signal from a
gate 220 are provided to one set of inputs. The frame sync signal and CFS
signal are provided to another set of signals inputs. The composite sync
and line sync are provided to a third set of inputs and the index signal
and not inverted CIN signal to the fourth set of inputs. One of the two
sets of inputs is selected in accordance with a command labeled
"composite" on line 235. When composite video is present, i.e., when
interlaced scan is being used, this signal will cause the outputs of pulse
shaping and regeneration circuit 215 to be used. Where a sequential scan
camera is used, it will cause the signals on lines 221, 223 and 225 to be
used. These signals are provided as outputs through line drivers 237 to
the remainder of the system.
FIG. 5 is a block diagram of the digitizer interface. This interface is
actually more than a digitizer interface. It interfaces the system not
only with the digitizer but with the output real time output monitor 39 of
FIG. 1, provides test patterns and generates various types of control and
synchronation signals for use throughout the system. It also does various
types of input and output conversions and provides the output to the
display through a digital-to-analog converter. Also included in this
section of the system and used therein are DMA, i.e., Direct Memory
Access, inputs from the host processor which configure the system and set
it up for the type of operation desired.
Referring to the upper left-hand corner of the Figure, are located blocks
301 and 303. Block 301 is a sync-pulse to end of blanking delay counter.
Block 303 is analog-to-digital converter control logic. A-D control logic
303 receives as one input the data-ready signal of the line 207. Adjacent
lines 207, bus 209, to which a signal from the logic circuit 303 is added,
is visible. Adjacent that, the "composite" output which controls the
multiplexer 233 of FIG. 4, on line 235 is visible. Directly below that
line is the encode line 205 discussed above in connection with FIG. 4. The
"composite" signal on line 235 is obtained from a control register 305
which receives an input from the DMA bus. When the control register is
selected, by the signal labeled FNLT-4L, the values on the DMA bus are
stored in the control register providing control information. On the other
hand, when signal FNLT3L is present information is loaded into the address
register. This includes the words, "Incount" and "outcount" "In count"
indicates when it is time to begin inputting to the system, i.e., to begin
using the input on bus 209 and processing it.
The conversion in the analog-to-digital converter 201 of FIG. 4, was
carried out in response to the encode signal 205. The encode signal
consists of a pulse train having either a frequency of 13 MHz obtained
from an oscillator 317 or 10 MHz obtained from an oscillator 319. Which of
the two rates are provided on the line 205 is determined by the input
designated "Noninter" on a line 321 to a rate select multiplexer 323. The
reason for this is that, as explained above, if noninterlaced information
is being provided, it is in a 512.times.512 pixel format, i.e., it has a
1:1 aspect ratio. The normal interlaced scan, however, has a 4:3 aspect
ratio. Because of this, and since processing is done at the 10 MHz rate,
the input rate must be accellerated by a ratio of 4/3 or to 13 MHz. Thus,
to scan properly this higher frequency must be used but delay counter 301
must delay until the 85th pixel is reached as described above.
The data from the analog-to-digital converter is provided as an input to a
data select multiplexer 325. The data select multiplexer can select data
from four separate inputs. One input, bus 209 is coupled to the
analog-to-digital converter and a second 327 is coupled to a spare
external input 329. Third and fourth buses are coupled to RAM control
logic 331 and an exclusive OR gate checker board inverter 333. Which of
the inputs is selected is determined by a two bit control signal from
control register 305 called "mode" which is provided as an input to the
multiplexer 325 on line 335. The "mode" input of line 335 is also an input
to a sync-select multiplexer 337 at the left-hand side of the Figure. The
sync-select multiplexer has four, three line inputs. These are,
respectively, a noninterlace RAM input, an analog-to-digital input, a
spare external input and an interlace RAM input. In the case of the
analog-to-digital converter, the outputs which are provided as inputs are
the outputs from drivers 237 described in connection with FIG. 4.
For the moment, we will assume that the analog-to-digital converter has
been selected. The 10 MHz oscillator 319 and 13 MHz oscillator 317 are
controlled by an output from clock control logic 339 on line 341. This
determines when these keyed oscillators are turned on and turned off to
read in data. Which of these is selected will, of course, be determined by
whether or not there is a interlaced or noninterlaced input. Thus, the
noninterlaced control signal from control register 305 is provided on a
line 342 into an odd/even logic block 343 where it is combined with a
first output of the sync-select multiplexer, the output corresponding to
the index signal or representing field switchover. The field sync and line
sync are provided as inputs to a block 345 labeled "delay from field sync
to first valid line." This is a delay which is controlled by additional
control signals from control register 305 on lines 347, 348 and 349
labeled "delay start," "field zero delay" and "field one delay," the last
two representing the odd-and-even or even-and-odd field delays,
respectively. These are delays which are programmable through the host
processor and the control register, each having four bits of data to take
into account system delays. Thus, in dependence on these inputs, there is
a start delay and a delay in each of the two separate fields. At the
required time after the desired delay, an output signal is provided to
clock-control logic 339 on line 350.
As indicated, an output of the control logic 303 on line 313 is added on to
the 10 bit bus 209. This is, in effect, a signal at the pixel or data
rate, is also provided and corresponds, in frequency, to the data-ready
signal on line 207. Also provided through the multiplexer 325 is the line
sync signal. For a video input, the line sync is the signal "DSYNC" which
is delayed to take into account the delay necessary in converting to a
square image. These pixel rate and line sync signals out of the
multiplexer 325 are provided, respectively, to a line counter 351 and a
pixel counter 353. The output of the pixel counter is provided to an
end-of-line detector 355 and the outputs of the line counter 351 to an
end-of-frame detector 357 and an end-of-field detector 358. The outputs of
each of these detectors provide inputs to the clock control logic. Thus,
the clock control logic, having enabled the necessary clock 317 or 319
after the programmed delay, continues to enable the oscillator until the
end of a line is reached. After the end of the line, there is a certain
delay or retrace time. At the end of this time, the oscillator is, again,
enabled. If interlace is in use, it is necessary to detect the end of the
field for vertical retrace.
Similarly, it is necessary to detect the end of the frame whether it be
interlaced or noninterlaced to allow for vertical retrace. Thus, the clock
control logic uses the signals from the three detectors 355, 357 and 358,
along with the delay control signals on line 350, to turn the clock 317 or
319 on and off to read the data in at the desired times and the desired
rates. The data comes out of the multiplexer on 325 on line 361. In one
mode of operation known as "bypass" and controlled by a "normal/bypass"
control signal from the control register 305 on line 362, the data is
coupled directly through a series of drivers 363 to an output data bus
364. A second input to this bus is on a bus 365 which is coupled through a
driver 366 to the bus 364. This is the processed data input.
Normally, however, data is supplied to steering logic 367 under control of
write control logic 368 which directs it into buffer member memories 370
and 371. Data is alternately put into one memory or the other with the
control of which memory is used done by means of a page swap control 373
which is driven by the end of line signal from end of line detector 355.
The write control logic receives the data ready signal and the line sync
signal from the multiplexer 325. It also receives the output of the pixel
counter 353 which is on a ten bit bus.
In the case of the interlaced camera input, as indicated above, delay
counter 301 generates a pulse DSYNC which is the line sync signal received
at write control logic 368. In the case of sequential scan this sync will
not be delayed to the same extent to permit inputting data as soon as the
line starts. In either case, the write control logic, responsive to this
signal and to the pixel count on line 369, will cause 512 pixels to be
read into the buffer memory 370 for each line. In the case of the
interlaced scan these are read in at the rate of 13 MHz and in the case of
sequential scan at the rate of 10 MHz. (AIK memory is provided to allow
expansion to 1024 lines of resolution). The major portion of the remainder
of the system operates at 8.33 MHz to permit operating continuously and at
a rate within the capabilities of available hardware. The system clock is
generated by 25 mHz crystal oscillator 380, the output of which is divided
by 3 in a divide by 3 counter 381 to provide an 8.33 mHz system clock
signal on line 379. This line along with the end of line and end of frame
signals from detectors 355 and 357 are inputs to bus timing module 377.
Bus timing logic outputs operate the read control logic 376 associated
with the steering logic 367 and 375, the portion 375 being at the output
of the buffer memories, to read out data on line 378. The reading out is
done at the rate of 8.33 mHz. Read control logic 376 counts the number of
pixels read out and provides the signal on line 379 as an input to bus
timing 377. Basically, the data on line 378 is read out continuously at
8.3 mMHz. It is possible to read it out at this slower rate because of the
continuous reading. The input takes place in bursts because of the retrace
in the case of the 10 mMHz signal and the retrace and the accelerated
input in the case of the 13 mMHz signal. The 10 data lines 378 are
combined with 3 synchronization lines on a bus 382, these being time sync,
frame sync and system clock, and provided as inputs to differential bus
drivers 383 at least one of which is enabled by a bus enable signal 385
obtained from the control register 305.
The third and fourth selections comprise selections of the noninterlace RAM
signal and the interlace RAM signal. These are signals used for test
purposes. In the case of the noninterlace RAM, the sync signals are
derived from the camera control logic 339. In the case of the interlace
RAM operation, the sync signals are obtained from an RS-170 timing
generator RAM 338. RS-170 is a standard television interlace scan. A 10
MHz oscillator 389 provides an output into a divide by 5 counter 390,
which then provides a 2 mMHz addressing signal into the timing generator
RAM 388. The RAM 388 in turn generates the field index, vertical drive and
horizontal drive signals which are provided as inputs to the sync selector
multiplexer 337 where they are selected and used in the output in the same
manner as the sync signals from the digitizer of FIG. 4.
Through provision of a control signal on line 341, the 10 mMHz keyed
oscillator is turned on and provides an input into the RAM control logic
331 which provides address bits 2-6 to a test pattern RAM 391. This
provides 5 bits of an 8 bit address. Additional bits of the address are
provided by a bit shift multiplexer 393 having as inputs the outputs of
line countr 351. When in the interlace mode every other line is skipped.
The selected RAM outputs are coupled through a serializer 394 and a
checker board inverter made of up exclusive OR gates to provide the data
output. The second input to exclusive OR gates is the 7th bit output of
the RAM control logic. The RAM stores a 128.times.128 pixel pattern. Thus,
these patterns must alternate and are in a 4.times.4 matrix with adjacent
patterns inverted by the checkerboard inverter.
In the case of non-interlaced operation, as indicated by the noninterlace
control signal input to the multiplexer 393, every line in sucession is
selected rather than every other line. In either case, the data finds its
way to bus 396 and then through the multiplexer 325 after which it is
treated in the manner described above. By having both the non-interlace
and interlace capability with the test pattern, the ability of the system
to operate with either type of input can, thus, be tested.
The final function of the digitizer interface is in the conversion of
processed digital information back into analog form for display. As noted
previously, this information appears on bus 364 and may, in some cases, be
simply the input information bypassing all processing. In any case, an
arrangement very much like that used in providing input data into the
processor is used in outputing it to the display. The data is coupled into
steering logic 401 which is under the control of write control logic 403.
Similarly, the output steering logic 405 is controlled by the read-control
logic 407. The reading and writing is done into and out of buffer memories
409 and 411 with, again, a page swap control 413 provided. Operation is
essentially as described above in connection with the buffer memories 370
and 371.
A frame processor read control 421 which also has as an input the output of
the 10 mMHz oscillator 389 provides outputs of line sync and frame sync to
the display and interlace frame processors described above in connection
with FIG. 2. Frame processor read control 421 performs functions somewhat
analogous to the clock-control logic 339 in that it relies | | |
