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Swap control apparatus for hierarchical memory system
   
Document Number
US Patent 4733367
Issued Date
March 22, 1988
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Abstract
In a multiple-block-per-entry buffer memory (BS) of the swap or store-in type, a swap-out buffer (SOB) having a capacity for at least a block is provided. On the occasion of replacing, a memory access sequence control responds to change bits and validity bits associated with an entry to be replaced as well as the block address designated for memory access so as to execute the data transfer from a main memory (MS) to BS in preference to the sweeping-out of data from BS to SOB so long as the block to be replaced need not be stored in MS. If the block to be replaced needs to be stored, the sweeping-out into SOB is executed with the utmost priority, and the data transfer from MS is then executed in preference to the sweeping-out of any other blocks to be stored into MS.
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Swap control apparatus for hierarchical memory system - US Patent 4733367 Drawing
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Number of Claims:
4
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Owner
Hitachi, Ltd. (Tokyo,JP)
Published
March 22, 1988
Application Number
06/795,452
Filed
November 6, 1985
US Classification
711/159   711/117
Int'l Classification
G06F   12/08   (20060101)  
Assistant Examiner
Attorney/Law Firm
Priority Data
Nov 07, 1984 [JP] 59-233328
USPTO Field of Search
364/2MSFile   364/9MSFile  
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Description
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