An improved digital delay generator (10) for producing an output pulse/signal a preselected time interval after an input pulse/signal. The digital delay generator (10) of the present invention includes a single auxiliary timer (24) which starts responsive to feeding an input pulse thereto. This auxiliary timer (24) is stopped in response to the first generated clock pulse occurring after the input pulse. The timer (24) is then restarted after a preselected number of cycles of the clock pulse such that the total delay between the input pulse (12) and the output pulse (36) is substantially equal to the insertion delay of the single auxiliary timer (24) plus the preselected delay of the single auxiliary timer plus the delay occasioned by the lapsing of the preselected number of cycles of the clock pulse.

A variable delay device includes a variable delay circuit (12) and a correction circuit (14). On the basis of output signals R and V from variable delay lines (30, 32) of the correction circuit, an output signal V.sub.L by which a control characteristic of a variable delay line (16) is made substantially linear is outputted to the variable delay circuit from a linearity detector (34) of the correction circuit. The output signals R and V are also applied to a variable range detector (36), and on the basis of an output of the detector (36), an output signal V.sub.r by which a variable range of the variable delay line (16) is made constant is outputted to the variable delay circuit (12) from a reference level generator (38) of the correction circuit. The output signal V.sub.L determines an input/output characteristic of a non-linear circuit (22) which is included in the variable delay circuit and modifies a variable amount control signal V.sub.d, and the output signal V.sub.r is added to an output signal of the non-linear circuit by an adder (24) included in the variable delay circuit, and an adder result is applied to the variable delay line (16) as a control signal therefor.

The delay period of a delay circuit is maintained, over time, near to a desired delay, by generating information representative of the present delay period of the delay circuit, and altering the delay period, from time to time during operation, based on the present delay information and the desired delay. The present delay is measured by a reference circuit having a delay characteristic corresponding to the delay characteristic of the delay circuit. Both the reference and multiple delay circuits are formed with the same configuration on a single integrated circuit.

A semiconductor delay circuit which can realize a fine delay time regulation pitch and can set a number of regulation steps is provided. A plurality of inverter tree circuit each having a plurality of propagation paths having delay times different with an equal pitch are connected in series and outputs of the propagation paths are selectively transmitted externally by a switch circuit.

A variable delay buffer circuit composed of a cascade of variable delay buffers, which realizes a delay in response to a delay control signal without any glitches. The delay buffers each have a selector circuit for selecting one of an input signal and a delayed signal produced by delaying in time the input signal in response to a delaying information. The delay buffers each contains a first control means and an output means. The first control means controls a timing of a input of the delaying information into the selector circuit in response to an external control signal. The output means outputs the control signal to by synchronized with an output signal from the selector circuit. Preferably, the first control means contains a latching means for latching the delay information and a second control means for controlling a timing in output of the delay information from the latching means in response to the control signal.