A memory architecture is provided to enable parallel access along any dimension of an n-dimensional data array. To enable parallel access of s data elements along any dimension, the data elements of n-dimensional data array are mapped to s parallel memory banks in such a way that consecutive s data elements along any dimension are mapped to different memory banks. This mapping is defined by two functions, which define the memory bank number and location within a memory bank for each data element in n-dimensional data array. The necessary and sufficient conditions, which the mapping functions should satisfy in order to enable parallel data access, are described. These generic function pairs are described for all combinations of (n, s). Two particular instances of the mapping, namely circular permutation (rotation) along 0.sup.th dimension and dyadic permutation along 0.sup.th dimension have been discussed in detail. The mapping defined as dyadic permutation along 0.sup.th dimension holds only for values of s, which is integer power of 2. The mapping defined as circular rotation holds for any integer value of s. For these mappings, the basic architecture as well as its extensions are discussed. The basic architecture is for n-dimensional data array which has only s data elements along each dimension, whereas the extensions are for data arrays with m data elements along each dimension under the constraint that m is an integer multiple of s.

A memory system is provided with two data buffers, respectively, in the row and column directions of a memory array. The system is capable of operating either one of the two data buffers as input/output buffers in accordance with reading or writing operations on the contents of the memory array. Outputs from the memory array are inverted to form an inverted array. All bits along respective columns of the array are ANDed together to obtain an ANDed bit value for each column of the inverted array.

A process of loading an image in the form of a bit map into a memory which can transfer data words in burst mode in either row or column direction. First, the memory is divided into two sections with odd words stored in one section, even in the other, which allows ping pong buffers to be reading one word from memory while the next is being accessed. Also, the page height is set to be an odd number of words. Therefore, when the entire page is read in or out, successive words in either the row or column direction will always be alternately odd and even. If a partial image is read into the memory, this odd and even relationship will also hold. If an image with an even number of rows is read in, in order to preserve the sequential odd-even sequence, in every other column of the original data successive words are swapped so that the word order becomes 1, 0, 3, 2, etc. Then the addresses are also generated in staggered order, so that the words go into the correct location in memory. In this way, the word order of loading and reading of data is always successively odd and even regardless of the size of the image.

A two-dimensional memory unit allowing two-dimensional data to be written and read along different axes. Memory blocks having numerous memory cells arranged along each of the axes, are located at respective memory addresses, and a number of such memory blocks are arranged along the respective axes. All the memory cells of any of the memory blocks are accessed at the same time. The memory cells for actually inputting and outputting data are selected by data input and ouput controls. Data are written or read out of all of the number of memory cells in a two-dimensional small area by one memory access and, therefore, rapidly with no regard to the direction of scanning which occurs along any of the different axes.

A memory cell is comprised of a cross-coupled master latch and a cross-coupled slave latch. The memory cell includes means for switching on and off power supplies connected to the master latch and the slave latch so as to control the direction of shift in a bidirectional shift. Data is shifted in a first direction when the power supply connected to the master latch is switched off, and data is shifted in a second direction when the power supply connected to the slave latch is switched off.