A system and method is disclosed for providing dynamic multimedia jitter buffer adjustment for packet-switched networks. The system temporarily stores an amount of incoming data, which is dynamically adjustable, for an amount of time before sending the data out in a more even stream. The system includes a decoder clock, a jitter buffer, a network jitter statistics collector, and a jitter buffer controller. The decoder clock indicates the arrival-time of the data at the system, while the network jitter statistics collector collects the playback-time of that data. By comparing the arrival-time and the playback-time, the jitter buffer controller determines whether the data arrived on schedule. Accordingly, the depth of the jitter buffer can be adjusted to accommodate the late or early arriving data.

A communication network (10) includes packet switching nodes (18) in which packets from high speed data links (20, 22) are switched onto a multiplicity of low speed data links (26). Each node (18) includes a bulk RAM (30) which has a section (32) dedicated to implementing a multiplicity of logically independent FIFO buffers. A routing controller (46) controls DMA transfers of packets into and out from appropriate FIFO buffers. Packets are transferred into respective FIFO buffers consecutively and transferred out from respective FIFO buffers interleaved together.

In a computer system, the flow of data from the execution unit to the cache 28 is enhanced by pairing individual, sequential longword write operations into a simultaneous quadword write operation. Primary and secondary writebuffers 50, 52 sequentially receive the individual longwords during first and second clock cycles and simultaneously present the individual longwords over a quadword wide bus to the cache 28. During the first clock cycle, when the cache 28 is not performing the quadword write operation, the cache 28 is free to perform the requisite lookup routine on the address of the first longword of data to determine if the quadword of address space is available in the cache. Thus, the flow of data to the cache 28 is maximized.

A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.

An apparatus and method for maintaining cache/main memory consistency in a data processing system including a write-through cache (14). For write operations of less than a word in length, the write data stored within a FIFO memory device 18 associated with a first bus agent reflects the result of a read/modify/write type of access wherein a byte or half word has been merged by a local processor 12 with a cache word. Memory control lines driven to a system bus 20 indicate to a memory controller 22 that a write operation is to be accomplished as a word write, thereby eliminating the additional time required to achieve a read/modify/write memory controller cycle. To prevent the occurrence of a problem wherein another bus agent, such as another CPU or an I/O device, writes to a system memory 24 during an interval of time that the word of data is temporarily buffered within the FIFO there is provided circuitry for detecting an external write made to the system memory. Circuitry is provided for changing the memory command lines to indicate, instead of a word write, a byte write or a half-word write operation. This causes the memory controller to operate only upon the portion of data word that was modified by the local processor and to perform a conventional read/modify/write type of cycle to merge the byte or half word with a word from main memory.