A semiconductor device comprises a semiconductor substrate of a first conductivity type, a well which is a second conductivity type, a buried layer, which is of the first conductivity type, and an insulating isolation layer formed extending to an upper surface of a side region of the well. The buried layer has a first portion of a higher dopant concentration than the semiconductor substrate and formed in a deep region of the semiconductor substrate directly below the well, and a second portion formed in a region of the substrate which is positioned higher than the region in which the first portion is formed. The first and second portions of the buried layer are formed integrally in a region of the semiconductor substrate which is directly below the insulating isolation layer, surround the well within the semiconductor substrate, and have a high concentration of a dopant that is of the first conductivity type at a position which is directly below the insulating isolation layer. A transistor of the first conductivity type is formed at the well and a transistor of the second conductivity type is formed in the semiconductor substrate above the second portion of the buried layer.

In a method of manufacturing CMOS transistors, a well that is of a second conductivity type is formed in a semiconductor substrate of a first conductivity type and is surrounded by a high concentration buried layer of the first conductivity type which completely extends around and below the well, and which also constitutes wells of the first conductivity type. The high-concentration buried layer is formed by a self-aligned process, and the potential of the buried layer can be easily fixed from the top of the semiconductor substrate so that a high degree of resistance is obtained to CMOS latch-up.

Provided with a semiconductor device which is adopted to reduce the resistance of a well without the need to increase the concentration of dopants in forming the well by depositing conductive layer patterns and then growing an epitaxial layer on the conductive layer patterns, the semiconductor device including: conductive layer patterns formed on a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate and the conductive layer patterns; well regions formed in the semiconductor layer and the semiconductor substrate such that the conductive layer patterns are positioned at the bottoms of the well regions; and gate and source/drain electrodes formed on the well regions, and a method for fabricating the semiconductor device including the steps of: forming conductive layer patterns on a semiconductor substrate; forming a semiconductor layer on the semiconductor substrate including the conductive layer patterns; forming well regions in the semiconductor layer and the semiconductor substrate such that the conductive layer patterns are positioned at the bottom of the well regions; and forming gate and source/drain electrodes on the well regions.