A direct access filter includes an array of memories for processing digital signal data from signal sources such as sensors in a radar system. The parameters in a packet are tested against a predetermined set of corresponding data. Each set of data can be considered as a window. If the value of each tested parameter falls within the window, then the packet matches the filter criteria. There can be several sets of filter criteria, and hence all sets must be sequentially tested. Upon finding a filter match, two actions can result: "excision", wherein occurrence of a match results in that parameter packet being discarded from the data flow, or "track", which results in the transfer of the parameter data to a follow on processor. Processing time is saved when a match occurs and no updating of previous data is required.
The disclosure teaches a reconfigurable parameter filter of the type useful in radar ESM systems. The filter has first and second sections adapted to be supplied with first and second binary numbers, respectively. Each section consists of upper and lower limit storage registers and upper and lower limit comparators, the comparators being coupled to an AND gate and responsive to the respective binary number to enable the AND gate if the value of the signal lies within the window set by the storage registers. The two sections can operate on two independent data words or can be coupled to act as a unit on one data word under the control of a mode selecting circuit. As a result the same standardized circuit module can process either one high precision parameter number or two low precision parameter numbers.
A polarity detector 100 wherein bistables 105 and 107 selectively sample the sequence of pulses and store samples. The samples and the output signal 125, stored by the bistable 109, are compared by the logic circuit 108. When the stored samples have identical polarity and the polarity of the output signal 125 is not identical to the polarity of the samples, then the polarity of the output signal 125 is changed to the polarity of the samples. However, when the polarity of the samples and that of the output signal 125 are not identical, then the polarity of the output signal 125 remains unchanged. In addition, when the polarity of the stored samples are not identical, the polarity of the output signal 125 remains unchanged. Hence, the polarity of the output signal 125 indicates the polarity of the sequence of pulses 120.
An apparatus for detecting a succession of data comprises a comparator storing first and second data, respectively, a first flip-flop having an input supplied with the first data from the comparator, a gate having inputs supplied, respectively, with the second data from the comparator and the output of the first flip-flop, a second flip-flop having an input supplied with the output of the gate, and a pulse generator operating in synchronism with input data to produce a shift pulse signal delayed relative to the input data for a time required for the operation of the comparator. The shift pulse signal is applied to the inputs of the first and second flip-flops to thereby cause the output of the first flip-flop to be shifted to the second flip-flop only when the input data corresponding to the first and second data, respectively, are applied to the comparator. Thus, continuity in the input data can be detected. By providing additionally a selector on the output side of the flip-flops, identification of the data contained in the input data string can be accomplished.
A tone signal detecting circuit includes a sampling circuit, a storage circuit, and a comparing circuit. The sampling circuit samples a tone signal at a sampling rate N times (N is a natural number) higher than a frequency f of the one signal. The storage circuit stores M (M is a natural number) latest values of time series data from the sampling circuit. The comparing circuit compares a plurality of polarity patterns expected on the basis of a tone signal with polarity patterns stored in the storage circuit and outputting coincidence outputs.
A combinational logic circuit for determining whether an address is inside or outside a range at least partially defined by a control address bit. The logic circuit includes combinational logic connected to an address bit line for receiving the address bit being tested and connected to a control address bit line for receiving the control address bit at least partially defining the range. The combinational logic is configured to produce a signal indicating whether the address bit being tested and the control address bit at least partially defining the range are equal. The combinational logic is also configured to produce a signal representing a mathematical relation between the address bit being tested and the control address bit at least partially defining the range. The mathematical relation identifies whether the address bit being tested is inside or outside the range at least partially defined by the control address bit.
