A nest level judging device is operable in response to tokens each of which is given a nest level selected from first through N-th nest levels as a selected level and each of which comprises a data length code and a data identifier code including a nest bit. A detecting circuit (50) detects the nest bit to produce a nest bit detection signal. Responsive to selection signals, a selecting circuit (30) delivers the data length codes of the respective tokens as first through N-th data codes. A processing circuit (40) processes the first through the N-th data codes into a processed signal which is N bits long. Responsive to the nest bit detection signal and the first through the N-th data codes, a level decision circuit (60) decides a decided nest level indicative of, as the selected level, one of the first through the N-th nest levels that is selected as the selected level. The level decision circuit (60) supplies the decided nest level as one of the selection signals to the selection circuit.

When a nest level judging device is supplied with tokens each of which has a nest level selected from first through N-th nest levels as a selected level and each of which comprises a header and a data set where the header comprises a data length code and a data identifier code including a nest bit, a counter (31) produces an address signal for specifying starting and end addresses of each of the tokens and a varying address varying from the starting address to the end address. Supplied with the header, a header register (32) produces a data length signal representative of the data length code and a nest bit signal which represents that the each of the tokens is nested in the data set thereof. Supplied with the address signal and the data length signal, an end address calculator (33) calculates the end address of the respective tokens and produces an end address signal representative of the end address. Responsive to selection signals, a selector (34) delivers the end addresses of the respective tokens as first through N-th end addresses. Supplied with the nest bit signal, the address signal, and the first through the N-th end addresses, a decision unit (35) decides a decided nest level, indicative of one of the first through the N-th nest levels that is selected as the selected level. The level decision unit delivers the decided nest level as one of the selection signals to the selector.

A bus relay apparatus includes a counting unit and a switching unit. The counting unit counts polling signals transmitted from a bus controller present in a first group of a plurality of grouped data communication processors. The switching unit switches a bus direction in accordance with the count of the counting unit.

In a token train retrieval device including a memory device (24) for memorizing a plurality of tokens as stored tokens each of which starts at a starting address and ends at an end address and each of which has a nest level selected from first through N-th nest levels and comprises a header and a data set where the header comprises a data length code and a data identifier code including a nest bit, a retrieval condition memory (25) memorizes a retrieval condition as a stored condition. Supplied with the header, a header register (26) holds the data length code, the data identifier code, and the nest bit as a held data length code, a held data identifier code, and a held nest bit. Responsive to the held data identifier code and a decided nest level, a checking circuit (27) checks whether or not the stored condition is satisfied to produce a matching signal when the stored condition is satisfied. An intra-train address generating circuit (29) generates an intra-train address variable in response to the matching signal, the held nest bit, and the held data length code. By using the intra-train address and the held data length code, an end address calculating circuit (30) calculates the end address of each token as a calculated address. By using the calculated address, the intra-train addresses, and the held nest bit, a nest level decision circuit (31) decides the decided nest level indicative of one of the first through the N-th nest levels.

In a token train retrieval device including a memory device (24) for memorizing a plurality of tokens each of which starts at a starting address and ends at an end address and each of which has a nest level selected from a plurality of nest levels and comprises a header and a data set where header comprises a data length code and a data identifier code including a nest bit, a retrieval condition memory (25) memorizes a retrieval condition including a plurality of designated nest level codes and a plurality of designated identifier codes. A header register (26) holds the data length code, the data identifier code, and the nest bit as a held data length code, a held data identifier code, and a held nest bit. Responsive to the held data length code, a supplied header, and a decided nest level code, a checking circuit (27) produces a matching signal when the retrieval condition is satisfied. An intra-train address generating circuit (29) generates an intra-train address variable in accordance with the matching signal and the held data length code. Supplied with the intra-train address and the held data length code, an end address calculating circuit (30) calculates the end address of each token as a calculated address. Responsive to the intra-train address, the calculated address, and the held nest bit, a nest level decision circuit (31) supplies the checking circuit with the decided nest level code indicative of one of the nest levels.